-- Xilinx Vhdl produced by program ngd2vhdl E.35
-- Command: -w regex_app.ngd regex_app_sim.vhd 
-- Input file: regex_app.ngd
-- Output file: regex_app_sim.vhd
-- Design name: regex_app
-- Xilinx: C:/Xilinx
-- # of Entities: 1
-- Device: v2000efg680-6

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity regex_app is
  port (
    sod_appl_in : out STD_LOGIC; 
    dataen_out_appl : in STD_LOGIC := 'X'; 
    reset_l : in STD_LOGIC := 'X'; 
    dataen_appl_in : out STD_LOGIC; 
    tca_out_appl : out STD_LOGIC; 
    tca_appl_in : in STD_LOGIC := 'X'; 
    sod_out_appl : in STD_LOGIC := 'X'; 
    eof_out_appl : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    sof_out_appl : in STD_LOGIC := 'X'; 
    ready_l : out STD_LOGIC; 
    eof_appl_in : out STD_LOGIC; 
    sof_appl_in : out STD_LOGIC; 
    enable_l : in STD_LOGIC := 'X'; 
    d_out_appl : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    d_appl_in : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    matched : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end regex_app;

architecture STRUCTURE of regex_app is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal regex_in_2_1_Q : STD_LOGIC; 
  signal regex_in_2_4_Q : STD_LOGIC; 
  signal regex_in_2_2_Q : STD_LOGIC; 
  signal regex_in_2_5_Q : STD_LOGIC; 
  signal reset_l_0 : STD_LOGIC; 
  signal reset_l_1 : STD_LOGIC; 
  signal reset_l_2 : STD_LOGIC; 
  signal dataen_out : STD_LOGIC; 
  signal eof_out : STD_LOGIC; 
  signal sod_out : STD_LOGIC; 
  signal sof_out : STD_LOGIC; 
  signal reset_l_i_8 : STD_LOGIC; 
  signal reset_l_i_7 : STD_LOGIC; 
  signal reset_l_i_6 : STD_LOGIC; 
  signal reset_l_i_5 : STD_LOGIC; 
  signal reset_l_i_4 : STD_LOGIC; 
  signal reset_l_i_3 : STD_LOGIC; 
  signal reset_l_i_2 : STD_LOGIC; 
  signal reset_l_i_1 : STD_LOGIC; 
  signal reset_l_i : STD_LOGIC; 
  signal regular_expression_machine5_N_2119 : STD_LOGIC; 
  signal regular_expression_machine5_N_2047 : STD_LOGIC; 
  signal G_723_sx : STD_LOGIC; 
  signal G_723 : STD_LOGIC; 
  signal regular_expression_machine5_N_2099 : STD_LOGIC; 
  signal regular_expression_machine5_N_2101 : STD_LOGIC; 
  signal regular_expression_machine5_N_2102 : STD_LOGIC; 
  signal regular_expression_machine5_N_2083 : STD_LOGIC; 
  signal cntrlr_out_state_8_Q : STD_LOGIC; 
  signal G_702 : STD_LOGIC; 
  signal G_703 : STD_LOGIC; 
  signal G_704 : STD_LOGIC; 
  signal G_705 : STD_LOGIC; 
  signal G_706 : STD_LOGIC; 
  signal G_707 : STD_LOGIC; 
  signal G_708 : STD_LOGIC; 
  signal G_709 : STD_LOGIC; 
  signal cntrlr_out_buf_out_34_Q : STD_LOGIC; 
  signal G_711 : STD_LOGIC; 
  signal cntrlr_fifo_we_2 : STD_LOGIC; 
  signal cntrlr_out_state_2_Q : STD_LOGIC; 
  signal cntrlr_out_buf_out_32_Q : STD_LOGIC; 
  signal G_715 : STD_LOGIC; 
  signal cntrlr_match_fifo_un1_rddone_buf : STD_LOGIC; 
  signal cntrlr_match_fifo_rddone_buf : STD_LOGIC; 
  signal G_716 : STD_LOGIC; 
  signal G_717 : STD_LOGIC; 
  signal cntrlr_match_fifo_un1_tail_19_c2 : STD_LOGIC; 
  signal G_718 : STD_LOGIC; 
  signal G_719 : STD_LOGIC; 
  signal regular_expression_machine5_N_2085 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_5_Q : STD_LOGIC; 
  signal regex_en_2 : STD_LOGIC; 
  signal G_727 : STD_LOGIC; 
  signal regex_restart : STD_LOGIC; 
  signal regular_expression_machine2_N_639 : STD_LOGIC; 
  signal G_730 : STD_LOGIC; 
  signal regular_expression_machine2_N_668 : STD_LOGIC; 
  signal G_731 : STD_LOGIC; 
  signal regular_expression_machine2_N_696 : STD_LOGIC; 
  signal G_732 : STD_LOGIC; 
  signal regular_expression_machine2_N_709 : STD_LOGIC; 
  signal G_733 : STD_LOGIC; 
  signal regular_expression_machine2_N_596 : STD_LOGIC; 
  signal G_734 : STD_LOGIC; 
  signal regular_expression_machine0_N_688 : STD_LOGIC; 
  signal G_736 : STD_LOGIC; 
  signal regular_expression_machine0_N_717 : STD_LOGIC; 
  signal G_737 : STD_LOGIC; 
  signal regular_expression_machine0_N_746 : STD_LOGIC; 
  signal G_738 : STD_LOGIC; 
  signal regular_expression_machine0_N_772 : STD_LOGIC; 
  signal G_739 : STD_LOGIC; 
  signal regular_expression_machine0_N_638 : STD_LOGIC; 
  signal G_740 : STD_LOGIC; 
  signal cntrlr_N_811_1_i : STD_LOGIC; 
  signal cntrlr_out_state_0_Q : STD_LOGIC; 
  signal cntrlr_un20_dataen_out_6 : STD_LOGIC; 
  signal N_816_i : STD_LOGIC; 
  signal regular_expression_machine5_N_2098 : STD_LOGIC; 
  signal state_ns_246_0_and2_2_514 : STD_LOGIC; 
  signal regular_expression_machine5_N_2215 : STD_LOGIC; 
  signal N_826_2 : STD_LOGIC; 
  signal regular_expression_machine5_N_2094 : STD_LOGIC; 
  signal state_ns_246_0_and2_1_679 : STD_LOGIC; 
  signal regular_expression_machine5_N_1470 : STD_LOGIC; 
  signal G_724 : STD_LOGIC; 
  signal regular_expression_machine5_N_2092 : STD_LOGIC; 
  signal regular_expression_machine5_N_2140 : STD_LOGIC; 
  signal regular_expression_machine5_N_2126 : STD_LOGIC; 
  signal N_827_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_3_Q : STD_LOGIC; 
  signal G_725 : STD_LOGIC; 
  signal regular_expression_machine5_N_2086 : STD_LOGIC; 
  signal regular_expression_machine5_N_2087 : STD_LOGIC; 
  signal state_ns_322_0_and2_1_678 : STD_LOGIC; 
  signal regular_expression_machine5_N_2044 : STD_LOGIC; 
  signal G_726 : STD_LOGIC; 
  signal cntrlr_out_state_11_Q : STD_LOGIC; 
  signal cntrlr_fifo_empty : STD_LOGIC; 
  signal N_812_1 : STD_LOGIC; 
  signal cntrlr_mfifo_avail : STD_LOGIC; 
  signal G_710 : STD_LOGIC; 
  signal regex_en_0_0_and2_1_226 : STD_LOGIC; 
  signal cntrlr_N_1066 : STD_LOGIC; 
  signal regex_en_0_0_and2_0_208 : STD_LOGIC; 
  signal regex_en_0_0_and2_2_206 : STD_LOGIC; 
  signal G_713 : STD_LOGIC; 
  signal regular_expression_machine0_N_920_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_288 : STD_LOGIC; 
  signal regular_expression_machine6_N_308 : STD_LOGIC; 
  signal regular_expression_machine6_N_308_fast : STD_LOGIC; 
  signal regular_expression_machine6_N_308_rep1 : STD_LOGIC; 
  signal regular_expression_machine0_N_907_2 : STD_LOGIC; 
  signal cntrlr_N_882_1_i_2 : STD_LOGIC; 
  signal G_1_fast : STD_LOGIC; 
  signal regular_expression_machine6_N_307 : STD_LOGIC; 
  signal regular_expression_machine6_N_308_1 : STD_LOGIC; 
  signal regex_en : STD_LOGIC; 
  signal regular_expression_machine3_N_394_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_340_2 : STD_LOGIC; 
  signal regular_expression_machine7_N_344 : STD_LOGIC; 
  signal regular_expression_machine3_N_361 : STD_LOGIC; 
  signal regular_expression_machine1_N_520 : STD_LOGIC; 
  signal regular_expression_machine7_N_328 : STD_LOGIC; 
  signal regular_expression_machine1_N_561 : STD_LOGIC; 
  signal regular_expression_machine1_N_443 : STD_LOGIC; 
  signal regular_expression_machine6_N_342_2 : STD_LOGIC; 
  signal regular_expression_machine7_N_322_1 : STD_LOGIC; 
  signal regular_expression_machine3_N_418 : STD_LOGIC; 
  signal regular_expression_machine1_N_491_3 : STD_LOGIC; 
  signal regular_expression_machine6_N_310 : STD_LOGIC; 
  signal regular_expression_machine6_N_311 : STD_LOGIC; 
  signal regular_expression_machine7_N_104_1 : STD_LOGIC; 
  signal regular_expression_machine1_N_433_i : STD_LOGIC; 
  signal regular_expression_machine2_N_595_1 : STD_LOGIC; 
  signal regex_en_1 : STD_LOGIC; 
  signal cntrlr_N_882_1_i_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_374_1 : STD_LOGIC; 
  signal regular_expression_machine3_N_388_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_341_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_339_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_375_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_288_rep1 : STD_LOGIC; 
  signal regular_expression_machine6_N_329_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_340_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_367_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_394 : STD_LOGIC; 
  signal regular_expression_machine7_N_368_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_271_2 : STD_LOGIC; 
  signal regular_expression_machine7_N_365_1 : STD_LOGIC; 
  signal cntrlr_N_882_1_i : STD_LOGIC; 
  signal regular_expression_machine0_G_88_s : STD_LOGIC; 
  signal regular_expression_machine0_G_109_sx : STD_LOGIC; 
  signal regular_expression_machine0_N_965 : STD_LOGIC; 
  signal regular_expression_machine0_G_97_sx : STD_LOGIC; 
  signal regular_expression_machine0_N_953 : STD_LOGIC; 
  signal regular_expression_machine0_N_946 : STD_LOGIC; 
  signal regular_expression_machine0_G_127_bm_1 : STD_LOGIC; 
  signal regular_expression_machine0_N_962 : STD_LOGIC; 
  signal regular_expression_machine0_G_127_bm : STD_LOGIC; 
  signal regular_expression_machine0_N_947 : STD_LOGIC; 
  signal regular_expression_machine0_N_884 : STD_LOGIC; 
  signal regular_expression_machine0_N_897 : STD_LOGIC; 
  signal regular_expression_machine0_G_127_am : STD_LOGIC; 
  signal regular_expression_machine0_N_895 : STD_LOGIC; 
  signal regular_expression_machine0_N_708 : STD_LOGIC; 
  signal regular_expression_machine0_N_958 : STD_LOGIC; 
  signal regular_expression_machine0_N_882 : STD_LOGIC; 
  signal regular_expression_machine0_N_964 : STD_LOGIC; 
  signal regular_expression_machine0_N_952 : STD_LOGIC; 
  signal regular_expression_machine0_N_945 : STD_LOGIC; 
  signal regular_expression_machine0_state_ns_30_s : STD_LOGIC; 
  signal regular_expression_machine0_G_87_s : STD_LOGIC; 
  signal regular_expression_machine0_G_94_s : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_710 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_180_sx : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_744 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_922 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_634 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_224_i_55_1 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_224_i_55 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_57_bm_1 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_57_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_624 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_920 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_722 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_610 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_637 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_679 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_921 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_671 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_666 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_919 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_827 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_127_0_and2_0_619 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_693 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_316_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_316_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_757 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_216_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_216_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_761 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_771 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_209_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_209_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_635 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_707 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_737 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_199_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_199_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_759 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_750_1 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_731 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_745 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_741 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_177_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_177_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_701 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_736 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_172_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_172_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_280_278 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_246_263 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_167_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_167_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_729 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_645 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_603 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_298_605 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_725 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_151_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_151_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_715 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_706 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_697 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_141_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_141_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_140_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_140_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_139_0_683 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_918 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_314_671 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_138_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_138_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_704 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_659 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_687 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_119_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_119_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_685 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_43 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_103_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_103_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_658 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_90_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_90_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_914 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_656 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_309_234 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_606 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_644 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_266_308 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_907 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_262_317 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_627 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_630 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_64_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_64_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_60_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_60_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_57_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_302_643 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_609 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_34_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_34_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_N_607 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_32_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_32_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_23_s : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_28_am : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_28_bm : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_312_642 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_89_0_and2_0_300 : STD_LOGIC; 
  signal regular_expression_machine0_state_h_state_ns_280_275 : STD_LOGIC; 
  signal regular_expression_machine1_N_560 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_4_Q : STD_LOGIC; 
  signal regular_expression_machine1_N_547 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_2_Q : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_16_Q : STD_LOGIC; 
  signal regular_expression_machine1_N_303 : STD_LOGIC; 
  signal regular_expression_machine1_N_431 : STD_LOGIC; 
  signal regular_expression_machine1_N_398_1 : STD_LOGIC; 
  signal regular_expression_machine1_N_468 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_12_Q : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_14_Q : STD_LOGIC; 
  signal regular_expression_machine1_N_521 : STD_LOGIC; 
  signal regular_expression_machine1_N_482_4 : STD_LOGIC; 
  signal regular_expression_machine1_N_484 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_6_Q : STD_LOGIC; 
  signal regular_expression_machine1_N_438 : STD_LOGIC; 
  signal regular_expression_machine1_N_442 : STD_LOGIC; 
  signal regular_expression_machine1_N_502 : STD_LOGIC; 
  signal regular_expression_machine1_G_200_280 : STD_LOGIC; 
  signal regular_expression_machine1_N_430 : STD_LOGIC; 
  signal regular_expression_machine1_G_198_235 : STD_LOGIC; 
  signal regular_expression_machine1_N_429 : STD_LOGIC; 
  signal regular_expression_machine1_N_428 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_11_20_498 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_0_and2_21_570 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_21_Q : STD_LOGIC; 
  signal regular_expression_machine1_N_525 : STD_LOGIC; 
  signal regular_expression_machine1_N_524 : STD_LOGIC; 
  signal regular_expression_machine1_N_509 : STD_LOGIC; 
  signal regular_expression_machine1_N_285 : STD_LOGIC; 
  signal regular_expression_machine1_G_221_119 : STD_LOGIC; 
  signal regular_expression_machine1_G_221_117 : STD_LOGIC; 
  signal regular_expression_machine1_G_239_135 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_0_and2_10_301 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_10_Q : STD_LOGIC; 
  signal regular_expression_machine1_N_555 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_12_20_420 : STD_LOGIC; 
  signal regular_expression_machine1_N_491 : STD_LOGIC; 
  signal regular_expression_machine1_N_488 : STD_LOGIC; 
  signal regular_expression_machine1_N_485 : STD_LOGIC; 
  signal regular_expression_machine1_N_470 : STD_LOGIC; 
  signal regular_expression_machine1_N_469 : STD_LOGIC; 
  signal regular_expression_machine1_N_467 : STD_LOGIC; 
  signal regular_expression_machine1_N_466 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_18_Q : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_20_578 : STD_LOGIC; 
  signal regular_expression_machine1_N_478 : STD_LOGIC; 
  signal regular_expression_machine1_un1_state_83_0_and2_581 : STD_LOGIC; 
  signal regular_expression_machine1_N_553 : STD_LOGIC; 
  signal regular_expression_machine1_N_554 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_20_64 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_20_65 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_20_66 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_2_20_527 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_3_20_438 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_20_69 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_0_20_366 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_20_70 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_20_72 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_97_i_and2_218 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_99_i_and2_222 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_3_20_435 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_2_20_524 : STD_LOGIC; 
  signal regular_expression_machine1_nxt_state_47_99_i_579 : STD_LOGIC; 
  signal regular_expression_machine1_N_59_i : STD_LOGIC; 
  signal regular_expression_machine1_N_401_i : STD_LOGIC; 
  signal regular_expression_machine1_N_398_i : STD_LOGIC; 
  signal regular_expression_machine1_N_513_i : STD_LOGIC; 
  signal regular_expression_machine1_GND : STD_LOGIC; 
  signal regular_expression_machine2_G_67_sx : STD_LOGIC; 
  signal regular_expression_machine2_G_83_sx : STD_LOGIC; 
  signal regular_expression_machine2_N_847 : STD_LOGIC; 
  signal regular_expression_machine2_G_82_243 : STD_LOGIC; 
  signal regular_expression_machine2_G_81_sx_0 : STD_LOGIC; 
  signal regular_expression_machine2_N_845 : STD_LOGIC; 
  signal regular_expression_machine2_N_831 : STD_LOGIC; 
  signal regular_expression_machine2_N_829 : STD_LOGIC; 
  signal regular_expression_machine2_G_76_sx : STD_LOGIC; 
  signal regular_expression_machine2_N_840 : STD_LOGIC; 
  signal regular_expression_machine2_G_76_fast_sx : STD_LOGIC; 
  signal regular_expression_machine2_G_76_fast : STD_LOGIC; 
  signal regular_expression_machine2_N_827 : STD_LOGIC; 
  signal regular_expression_machine2_G_81_sx : STD_LOGIC; 
  signal regular_expression_machine2_N_600 : STD_LOGIC; 
  signal regular_expression_machine2_N_557 : STD_LOGIC; 
  signal regular_expression_machine2_N_796 : STD_LOGIC; 
  signal regular_expression_machine2_G_90_am : STD_LOGIC; 
  signal regular_expression_machine2_G_90_bm : STD_LOGIC; 
  signal regular_expression_machine2_N_794 : STD_LOGIC; 
  signal regular_expression_machine2_N_579 : STD_LOGIC; 
  signal regular_expression_machine2_N_545 : STD_LOGIC; 
  signal regular_expression_machine2_N_844 : STD_LOGIC; 
  signal regular_expression_machine2_N_841 : STD_LOGIC; 
  signal regular_expression_machine2_G_2_fast : STD_LOGIC; 
  signal regular_expression_machine2_N_832 : STD_LOGIC; 
  signal regular_expression_machine2_state_ns_224_282 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_133_bm_1 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_198_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_G_3_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_133_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_230_475 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_61_1 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_60_sx_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_52_sx_0 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_220_sx_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_571 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_92_sx_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_92_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_587 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_62_bm_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_62_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_52_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_90_0_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_195_bm_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_195_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_643 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_48_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_575 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_47_0_and2_s : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_90_0_sx_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_818 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_617 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_8_sx : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_540 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_536 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_208_1 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_660 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_666 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_633 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_824 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_562 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_205_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_760 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_638 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_815 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_814 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_630 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_88_0_and2_0_602 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_613 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_218_273 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_685 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_732 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_205_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_649 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_644 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_195_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_682 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_707 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_694 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_700 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_706 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_187_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_187_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_651 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_274_0_and2_552 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_266_0_and2_496 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_181_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_181_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_676 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_550 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_175_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_175_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_286_504 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_690 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_679 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_693 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_569 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_689 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_688 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_167_am_0 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_167_bm_0 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_673 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_678 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_256_505 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_152_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_152_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_145_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_145_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_657 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_656 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_133_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_599 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_632 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_218_274 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_101_0_623 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_820 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_622 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_592 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_65_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_65_bm : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_590 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_563 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_551 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_589 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_62_am : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_260_572 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_101_0_and2_601 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_N_823 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_286_502 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_101_0_and2_0_599 : STD_LOGIC; 
  signal regular_expression_machine2_state_h_state_ns_101_0_622 : STD_LOGIC; 
  signal regular_expression_machine3_N_360 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_2_12_428 : STD_LOGIC; 
  signal regular_expression_machine3_N_390 : STD_LOGIC; 
  signal regular_expression_machine3_N_366 : STD_LOGIC; 
  signal regular_expression_machine3_G_238_1_0 : STD_LOGIC; 
  signal regular_expression_machine3_N_362 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_0_12_346 : STD_LOGIC; 
  signal regular_expression_machine3_N_375 : STD_LOGIC; 
  signal regular_expression_machine3_N_423 : STD_LOGIC; 
  signal regular_expression_machine3_N_401_1 : STD_LOGIC; 
  signal regular_expression_machine3_N_391_1 : STD_LOGIC; 
  signal regular_expression_machine3_N_391 : STD_LOGIC; 
  signal regular_expression_machine3_N_403 : STD_LOGIC; 
  signal regular_expression_machine3_N_390_6 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_2_12_426 : STD_LOGIC; 
  signal regular_expression_machine3_G_230_158 : STD_LOGIC; 
  signal regular_expression_machine3_G_230_157 : STD_LOGIC; 
  signal regular_expression_machine3_N_385 : STD_LOGIC; 
  signal regular_expression_machine3_N_359 : STD_LOGIC; 
  signal regular_expression_machine3_N_393_3 : STD_LOGIC; 
  signal regular_expression_machine3_N_420 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_13_Q : STD_LOGIC; 
  signal regular_expression_machine3_N_429 : STD_LOGIC; 
  signal regular_expression_machine3_N_427 : STD_LOGIC; 
  signal regular_expression_machine3_N_426 : STD_LOGIC; 
  signal regular_expression_machine3_N_424 : STD_LOGIC; 
  signal regular_expression_machine3_G_217 : STD_LOGIC; 
  signal regular_expression_machine3_N_414 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_5_Q : STD_LOGIC; 
  signal regular_expression_machine3_N_405 : STD_LOGIC; 
  signal regular_expression_machine3_N_404 : STD_LOGIC; 
  signal regular_expression_machine3_un1_state_49_0_and2_0_and2_500 : STD_LOGIC; 
  signal regular_expression_machine3_N_402 : STD_LOGIC; 
  signal regular_expression_machine3_N_401 : STD_LOGIC; 
  signal regular_expression_machine3_N_400 : STD_LOGIC; 
  signal regular_expression_machine3_N_399 : STD_LOGIC; 
  signal regular_expression_machine3_N_398 : STD_LOGIC; 
  signal regular_expression_machine3_N_387 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_1_12_450 : STD_LOGIC; 
  signal regular_expression_machine3_N_389 : STD_LOGIC; 
  signal regular_expression_machine3_G_47_i_0_415 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_2_12_424 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_4_12_516 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_4_12_519 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_4_12_520 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_4_12_523 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_12_624 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_12_626 : STD_LOGIC; 
  signal regular_expression_machine3_nxt_state_31_i_0_0_12_627 : STD_LOGIC; 
  signal regular_expression_machine3_N_43_i : STD_LOGIC; 
  signal regular_expression_machine3_N_251_i : STD_LOGIC; 
  signal regular_expression_machine3_N_253_i : STD_LOGIC; 
  signal regular_expression_machine3_N_131_i : STD_LOGIC; 
  signal regular_expression_machine3_N_419_i : STD_LOGIC; 
  signal regular_expression_machine3_GND : STD_LOGIC; 
  signal regular_expression_machine3_VCC : STD_LOGIC; 
  signal regular_expression_machine4_N_514 : STD_LOGIC; 
  signal regular_expression_machine4_N_503 : STD_LOGIC; 
  signal regular_expression_machine4_N_502 : STD_LOGIC; 
  signal regular_expression_machine4_N_482 : STD_LOGIC; 
  signal regular_expression_machine4_N_486 : STD_LOGIC; 
  signal regular_expression_machine4_N_487 : STD_LOGIC; 
  signal regular_expression_machine4_N_493 : STD_LOGIC; 
  signal regular_expression_machine4_N_494 : STD_LOGIC; 
  signal regular_expression_machine4_N_495 : STD_LOGIC; 
  signal regular_expression_machine4_N_513 : STD_LOGIC; 
  signal regular_expression_machine4_G_284 : STD_LOGIC; 
  signal regular_expression_machine4_N_473_4 : STD_LOGIC; 
  signal regular_expression_machine4_N_131_1 : STD_LOGIC; 
  signal regular_expression_machine4_N_492_2 : STD_LOGIC; 
  signal regular_expression_machine4_N_449 : STD_LOGIC; 
  signal regular_expression_machine4_N_453 : STD_LOGIC; 
  signal regular_expression_machine4_N_446 : STD_LOGIC; 
  signal regular_expression_machine4_N_442 : STD_LOGIC; 
  signal regular_expression_machine4_N_440 : STD_LOGIC; 
  signal regular_expression_machine4_N_438 : STD_LOGIC; 
  signal regular_expression_machine4_N_496 : STD_LOGIC; 
  signal regular_expression_machine4_N_436 : STD_LOGIC; 
  signal regular_expression_machine4_N_479 : STD_LOGIC; 
  signal regular_expression_machine4_N_516 : STD_LOGIC; 
  signal regular_expression_machine4_N_501 : STD_LOGIC; 
  signal regular_expression_machine4_G_293_131 : STD_LOGIC; 
  signal regular_expression_machine4_G_293_128 : STD_LOGIC; 
  signal regular_expression_machine4_N_492 : STD_LOGIC; 
  signal regular_expression_machine4_N_491 : STD_LOGIC; 
  signal regular_expression_machine4_un1_state_40_0_and2_0_and2_556 : STD_LOGIC; 
  signal regular_expression_machine4_N_489 : STD_LOGIC; 
  signal regular_expression_machine4_N_488 : STD_LOGIC; 
  signal regular_expression_machine4_un1_state_17_0_and2_0_and2_401 : STD_LOGIC; 
  signal regular_expression_machine4_N_485 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_11_192 : STD_LOGIC; 
  signal regular_expression_machine4_N_484 : STD_LOGIC; 
  signal regular_expression_machine4_N_481 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_10_16_351 : STD_LOGIC; 
  signal regular_expression_machine4_N_480 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_9_16_334 : STD_LOGIC; 
  signal regular_expression_machine4_N_475 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_3_16_509 : STD_LOGIC; 
  signal regular_expression_machine4_N_473 : STD_LOGIC; 
  signal regular_expression_machine4_N_470 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_16_418 : STD_LOGIC; 
  signal regular_expression_machine4_N_469 : STD_LOGIC; 
  signal regular_expression_machine4_G_299_211 : STD_LOGIC; 
  signal regular_expression_machine4_N_518 : STD_LOGIC; 
  signal regular_expression_machine4_N_499 : STD_LOGIC; 
  signal regular_expression_machine4_N_519 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_86 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_1_16_470 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_87 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_88 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_89 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_6_16_445 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_90 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_7_16_342 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_2_16_405 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_2_16_408 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_2_16_410 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_2_16_411 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_and2_3_16_507 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_645 : STD_LOGIC; 
  signal regular_expression_machine4_nxt_state_39_i_0_0_16_648 : STD_LOGIC; 
  signal regular_expression_machine4_N_51_i : STD_LOGIC; 
  signal regular_expression_machine4_N_131_i : STD_LOGIC; 
  signal regular_expression_machine4_N_423_i : STD_LOGIC; 
  signal regular_expression_machine4_N_135_i : STD_LOGIC; 
  signal regular_expression_machine4_N_504_i : STD_LOGIC; 
  signal regular_expression_machine4_GND : STD_LOGIC; 
  signal regular_expression_machine4_VCC : STD_LOGIC; 
  signal regular_expression_machine5_N_1898 : STD_LOGIC; 
  signal regular_expression_machine5_state_4_Q : STD_LOGIC; 
  signal regular_expression_machine5_state_2_Q : STD_LOGIC; 
  signal regular_expression_machine5_N_1989 : STD_LOGIC; 
  signal regular_expression_machine5_un10_state_1 : STD_LOGIC; 
  signal regular_expression_machine5_N_2127 : STD_LOGIC; 
  signal regular_expression_machine5_N_1891 : STD_LOGIC; 
  signal regular_expression_machine5_N_2243 : STD_LOGIC; 
  signal regular_expression_machine5_N_1877 : STD_LOGIC; 
  signal regular_expression_machine5_N_1903 : STD_LOGIC; 
  signal regular_expression_machine5_G_223_fast : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_184_0_653 : STD_LOGIC; 
  signal regular_expression_machine5_N_1722 : STD_LOGIC; 
  signal regular_expression_machine5_G_443_bm_sx : STD_LOGIC; 
  signal regular_expression_machine5_G_443_bm : STD_LOGIC; 
  signal regular_expression_machine5_N_1393 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_184_0_and2_0_607 : STD_LOGIC; 
  signal regular_expression_machine5_N_1805 : STD_LOGIC; 
  signal regular_expression_machine5_G_439_bm_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_350_0_608 : STD_LOGIC; 
  signal regular_expression_machine5_N_1564 : STD_LOGIC; 
  signal regular_expression_machine5_G_439_bm : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_350_0_609 : STD_LOGIC; 
  signal regular_expression_machine5_N_1298_3 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_350_0_and2_1_562 : STD_LOGIC; 
  signal regular_expression_machine5_state_0_Q : STD_LOGIC; 
  signal regular_expression_machine5_state_1_Q : STD_LOGIC; 
  signal regular_expression_machine5_N_1704 : STD_LOGIC; 
  signal regular_expression_machine5_N_1718 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_216_0_and2_136 : STD_LOGIC; 
  signal regular_expression_machine5_N_2124 : STD_LOGIC; 
  signal regular_expression_machine5_N_1752 : STD_LOGIC; 
  signal regular_expression_machine5_N_2113 : STD_LOGIC; 
  signal regular_expression_machine5_N_2114 : STD_LOGIC; 
  signal regular_expression_machine5_N_2128 : STD_LOGIC; 
  signal regular_expression_machine5_N_1908 : STD_LOGIC; 
  signal regular_expression_machine5_N_2116 : STD_LOGIC; 
  signal regular_expression_machine5_N_2237 : STD_LOGIC; 
  signal regular_expression_machine5_G_485_s : STD_LOGIC; 
  signal regular_expression_machine5_N_1717_i : STD_LOGIC; 
  signal regular_expression_machine5_N_2196 : STD_LOGIC; 
  signal regular_expression_machine5_N_2246 : STD_LOGIC; 
  signal regular_expression_machine5_N_2244 : STD_LOGIC; 
  signal regular_expression_machine5_N_2242 : STD_LOGIC; 
  signal regular_expression_machine5_N_2240 : STD_LOGIC; 
  signal regular_expression_machine5_N_2236 : STD_LOGIC; 
  signal regular_expression_machine5_N_2040_i : STD_LOGIC; 
  signal regular_expression_machine5_N_2050 : STD_LOGIC; 
  signal regular_expression_machine5_G_443_am : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_160_0_96 : STD_LOGIC; 
  signal regular_expression_machine5_N_1733 : STD_LOGIC; 
  signal regular_expression_machine5_G_440_am : STD_LOGIC; 
  signal regular_expression_machine5_G_440_bm : STD_LOGIC; 
  signal regular_expression_machine5_N_1832_1 : STD_LOGIC; 
  signal regular_expression_machine5_N_1854_1 : STD_LOGIC; 
  signal regular_expression_machine5_N_1848 : STD_LOGIC; 
  signal regular_expression_machine5_N_1847 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_296_0_641 : STD_LOGIC; 
  signal regular_expression_machine5_G_439_am : STD_LOGIC; 
  signal regular_expression_machine5_N_2043 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_337_0_666 : STD_LOGIC; 
  signal regular_expression_machine5_N_1830 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_337_0_663 : STD_LOGIC; 
  signal regular_expression_machine5_N_1856 : STD_LOGIC; 
  signal regular_expression_machine5_N_2111 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_397_3_0_and2_267 : STD_LOGIC; 
  signal regular_expression_machine5_N_1741 : STD_LOGIC; 
  signal regular_expression_machine5_N_1738 : STD_LOGIC; 
  signal regular_expression_machine5_N_2074 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_236_i_546 : STD_LOGIC; 
  signal regular_expression_machine5_N_2225 : STD_LOGIC; 
  signal regular_expression_machine5_N_1732 : STD_LOGIC; 
  signal regular_expression_machine5_N_1868 : STD_LOGIC; 
  signal regular_expression_machine5_N_1707 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_265_0_and2_1_373 : STD_LOGIC; 
  signal regular_expression_machine5_N_1710 : STD_LOGIC; 
  signal regular_expression_machine5_N_1912 : STD_LOGIC; 
  signal regular_expression_machine5_state_ns_435_0_and2_255 : STD_LOGIC; 
  signal regular_expression_machine5_N_1895 : STD_LOGIC; 
  signal regular_expression_machine5_un10_state : STD_LOGIC; 
  signal regular_expression_machine5_N_1884 : STD_LOGIC; 
  signal regular_expression_machine5_N_2208 : STD_LOGIC; 
  signal regular_expression_machine5_N_1883 : STD_LOGIC; 
  signal regular_expression_machine5_N_1879 : STD_LOGIC; 
  signal regular_expression_machine5_N_1993 : STD_LOGIC; 
  signal regular_expression_machine5_G_226_455 : STD_LOGIC; 
  signal regular_expression_machine5_G_484_s : STD_LOGIC; 
  signal regular_expression_machine5_G_487_s : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_184_0_653_1_0 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_184_0_653_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_279_0_and2_sx : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_and2_3_sx_sx : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_and2_3_sx : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_157_0_and2_252 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_157_0_and2_0_359 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_84_i_and2_sx : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1841 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1798 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2219 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_80 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_83_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_sx : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1511 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1840 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1838 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1837 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_265_0_674_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1831 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_265_0_674 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1303 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1807 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2102_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2057_2 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_633_1_0 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_76 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_633_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_633 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_and2_7_391 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_and2_3_279 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1507 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_634 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2063 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1671 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2156 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2222 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2229 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1816 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2070 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1436 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2212 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2213 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1774 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2210 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2209_2 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1291 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1821_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1852_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2075 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1495_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2226 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1493 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2080 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1534 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1367 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1858 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2079 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1772 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1462 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_71_am : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_71_bm : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1306 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_70_i_660 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1766 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_37_0_75 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_340_0_56 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2106_1 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_189_0_and2_1_394 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_246_0_and2_3_531 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_175_i_and2_312 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2069 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1844 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_and2_4_375 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_102_i_and2_7_390 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1799 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_and2_1_547 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1796 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_240_0_670 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1825 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_222_0_78 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_222_0_and2_3_443 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1452 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1435 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2095 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2093 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_316_0_639 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_316_0_and2_620 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2089 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1862 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1857 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_and2_2_331 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1794 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_37_0_and2_2_571 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1765 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1764 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_355_0_and2_563 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2104 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2105 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2106 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_108_i_and2_3_540 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_2107 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_222_0_and2_1_566 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1817 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1853 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1813 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_205_0_60 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1818 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1824 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_37_0_and2_357 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_283_0_and2_595 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_91 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_and2_6_343 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_92 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_and2_5_356 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_160_0_95 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_316_0_98 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_316_0_99 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_157_0_and2_250 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_240_0_and2_4_378 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_337_0_and2_1_400 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_246_0_and2_2_513 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_70_i_658 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_240_0_667 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_240_0_669 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_state_ns_108_i_690 : STD_LOGIC; 
  signal regular_expression_machine5_state_h_N_1951_i : STD_LOGIC; 
  signal regular_expression_machine6_N_269_i_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_312 : STD_LOGIC; 
  signal regular_expression_machine6_N_306 : STD_LOGIC; 
  signal regular_expression_machine6_N_269_i : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_and2_10_14_179_1_0 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_and2_10_14_175 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_and2_10_14_179 : STD_LOGIC; 
  signal regular_expression_machine6_N_258 : STD_LOGIC; 
  signal regular_expression_machine6_N_314 : STD_LOGIC; 
  signal regular_expression_machine6_N_316 : STD_LOGIC; 
  signal regular_expression_machine6_N_347_7 : STD_LOGIC; 
  signal regular_expression_machine6_G_176_171 : STD_LOGIC; 
  signal regular_expression_machine6_G_176_170 : STD_LOGIC; 
  signal regular_expression_machine6_N_309 : STD_LOGIC; 
  signal regular_expression_machine6_N_354 : STD_LOGIC; 
  signal regular_expression_machine6_N_353 : STD_LOGIC; 
  signal regular_expression_machine6_N_313 : STD_LOGIC; 
  signal regular_expression_machine6_N_298_1 : STD_LOGIC; 
  signal regular_expression_machine6_N_321 : STD_LOGIC; 
  signal regular_expression_machine6_N_340 : STD_LOGIC; 
  signal regular_expression_machine6_N_348 : STD_LOGIC; 
  signal regular_expression_machine6_N_352 : STD_LOGIC; 
  signal regular_expression_machine6_N_339 : STD_LOGIC; 
  signal regular_expression_machine6_N_338 : STD_LOGIC; 
  signal regular_expression_machine6_N_343 : STD_LOGIC; 
  signal regular_expression_machine6_N_341 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_54 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_53 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_575 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_52 : STD_LOGIC; 
  signal regular_expression_machine6_N_121 : STD_LOGIC; 
  signal regular_expression_machine6_N_326 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_and2_15_0_and2_0_and2_14_383 : STD_LOGIC; 
  signal regular_expression_machine6_N_342 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_48 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_50 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_and2_0_14_260 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_51 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_and2_9_14_248 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_and2_8_14_238 : STD_LOGIC; 
  signal regular_expression_machine6_nxt_state_35_i_i_0_14_573 : STD_LOGIC; 
  signal regular_expression_machine6_N_296_i : STD_LOGIC; 
  signal regular_expression_machine6_N_277_i : STD_LOGIC; 
  signal regular_expression_machine6_N_273_i : STD_LOGIC; 
  signal regular_expression_machine6_N_298_i : STD_LOGIC; 
  signal regular_expression_machine6_N_275_i : STD_LOGIC; 
  signal regular_expression_machine6_N_302_i : STD_LOGIC; 
  signal regular_expression_machine6_N_271_i : STD_LOGIC; 
  signal regular_expression_machine6_N_300_i : STD_LOGIC; 
  signal regular_expression_machine6_N_345_i : STD_LOGIC; 
  signal regular_expression_machine6_VCC : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_37 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_40_sx : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_40 : STD_LOGIC; 
  signal regular_expression_machine7_N_361 : STD_LOGIC; 
  signal regular_expression_machine7_N_338 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_41 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_43 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_46_sx : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_46 : STD_LOGIC; 
  signal regular_expression_machine7_N_371 : STD_LOGIC; 
  signal regular_expression_machine7_N_389 : STD_LOGIC; 
  signal regular_expression_machine7_N_331 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_37_1 : STD_LOGIC; 
  signal regular_expression_machine7_N_363 : STD_LOGIC; 
  signal regular_expression_machine7_N_358 : STD_LOGIC; 
  signal regular_expression_machine7_N_339 : STD_LOGIC; 
  signal regular_expression_machine7_N_329 : STD_LOGIC; 
  signal regular_expression_machine7_N_388 : STD_LOGIC; 
  signal regular_expression_machine7_N_391 : STD_LOGIC; 
  signal regular_expression_machine7_N_333 : STD_LOGIC; 
  signal regular_expression_machine7_N_382_2 : STD_LOGIC; 
  signal regular_expression_machine7_N_386 : STD_LOGIC; 
  signal regular_expression_machine7_N_381_2 : STD_LOGIC; 
  signal regular_expression_machine7_N_375 : STD_LOGIC; 
  signal regular_expression_machine7_N_335 : STD_LOGIC; 
  signal regular_expression_machine7_N_377 : STD_LOGIC; 
  signal regular_expression_machine7_N_390 : STD_LOGIC; 
  signal regular_expression_machine7_N_397 : STD_LOGIC; 
  signal regular_expression_machine7_N_353 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_0_0_and2_0_15_305 : STD_LOGIC; 
  signal regular_expression_machine7_N_336 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_15_Q : STD_LOGIC; 
  signal regular_expression_machine7_N_376 : STD_LOGIC; 
  signal regular_expression_machine7_N_330 : STD_LOGIC; 
  signal regular_expression_machine7_N_370_2 : STD_LOGIC; 
  signal regular_expression_machine7_N_365 : STD_LOGIC; 
  signal regular_expression_machine7_N_370 : STD_LOGIC; 
  signal regular_expression_machine7_N_369 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_13_Q : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_9_Q : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_and2_14_14_165 : STD_LOGIC; 
  signal regular_expression_machine7_N_355_6 : STD_LOGIC; 
  signal regular_expression_machine7_N_119 : STD_LOGIC; 
  signal regular_expression_machine7_un1_state_47_0_and2_0_and2_388 : STD_LOGIC; 
  signal regular_expression_machine7_N_374 : STD_LOGIC; 
  signal regular_expression_machine7_N_372_3 : STD_LOGIC; 
  signal regular_expression_machine7_N_355_8 : STD_LOGIC; 
  signal regular_expression_machine7_N_373 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_7_Q : STD_LOGIC; 
  signal regular_expression_machine7_N_381 : STD_LOGIC; 
  signal regular_expression_machine7_N_382 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_0_and2_0_and2_2_364 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_2_Q : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_14_39 : STD_LOGIC; 
  signal regular_expression_machine7_nxt_state_35_i_i_0_and2_14_14_162 : STD_LOGIC; 
  signal regular_expression_machine7_N_108_i : STD_LOGIC; 
  signal regular_expression_machine7_N_104_i : STD_LOGIC; 
  signal regular_expression_machine7_N_322_i : STD_LOGIC; 
  signal regular_expression_machine7_N_380_i : STD_LOGIC; 
  signal regular_expression_machine7_GND : STD_LOGIC; 
  signal regular_expression_machine7_VCC : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_0 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_0_0 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_1 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_2 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_3 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_4 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_5 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_6 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_7 : STD_LOGIC; 
  signal cntrlr_N_372_i : STD_LOGIC; 
  signal cntrlr_N_373_i : STD_LOGIC; 
  signal cntrlr_N_374_i : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_axb_3 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_axb_4 : STD_LOGIC; 
  signal cntrlr_N_375_i : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_axb_6 : STD_LOGIC; 
  signal cntrlr_GND : STD_LOGIC; 
  signal cntrlr_out_ptr_lcry : STD_LOGIC; 
  signal cntrlr_N_838_i : STD_LOGIC; 
  signal cntrlr_un1_reset_l_29_i : STD_LOGIC; 
  signal cntrlr_N_836_i : STD_LOGIC; 
  signal cntrlr_N_834_i : STD_LOGIC; 
  signal cntrlr_fsm_state_34_5_Q : STD_LOGIC; 
  signal cntrlr_fsm_state_34_4_Q : STD_LOGIC; 
  signal cntrlr_fsm_state_34_3_Q : STD_LOGIC; 
  signal cntrlr_fsm_state_34_2_Q : STD_LOGIC; 
  signal cntrlr_N_845 : STD_LOGIC; 
  signal cntrlr_N_828_i : STD_LOGIC; 
  signal cntrlr_fsm_state_34_12_Q : STD_LOGIC; 
  signal cntrlr_fsm_state_34_11_Q : STD_LOGIC; 
  signal cntrlr_fsm_state_34_10_Q : STD_LOGIC; 
  signal cntrlr_N_840_i : STD_LOGIC; 
  signal cntrlr_N_1105_i : STD_LOGIC; 
  signal cntrlr_N_1217_i : STD_LOGIC; 
  signal cntrlr_N_1194_i : STD_LOGIC; 
  signal cntrlr_un8_ready_l_NE_i : STD_LOGIC; 
  signal cntrlr_un8_ready_l_NE_i_i : STD_LOGIC; 
  signal cntrlr_buf_full6_NE : STD_LOGIC; 
  signal cntrlr_buf_full6_NE_i : STD_LOGIC; 
  signal cntrlr_prev_ptr_1_rep1 : STD_LOGIC; 
  signal cntrlr_N_868 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_axb_8 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_axb_7 : STD_LOGIC; 
  signal cntrlr_N_852 : STD_LOGIC; 
  signal cntrlr_N_890 : STD_LOGIC; 
  signal cntrlr_N_891 : STD_LOGIC; 
  signal cntrlr_fsm_state_34_0_and2_2_214 : STD_LOGIC; 
  signal cntrlr_N_856 : STD_LOGIC; 
  signal cntrlr_fsm_state_34_0_and2_0_10_189 : STD_LOGIC; 
  signal cntrlr_out_state_3_Q : STD_LOGIC; 
  signal cntrlr_un16_input_ptr_NE_2 : STD_LOGIC; 
  signal cntrlr_un16_input_ptr_NE_1 : STD_LOGIC; 
  signal cntrlr_un16_input_ptr_NE_4 : STD_LOGIC; 
  signal cntrlr_un16_input_ptr_NE_3 : STD_LOGIC; 
  signal cntrlr_un16_input_ptr_NE_7 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_6 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_7 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_4 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_5 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_2 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_3 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_1 : STD_LOGIC; 
  signal cntrlr_buf_full6_NE_7 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_7 : STD_LOGIC; 
  signal cntrlr_buf_full6_NE_2 : STD_LOGIC; 
  signal cntrlr_buf_full6_NE_1 : STD_LOGIC; 
  signal cntrlr_buf_full6_NE_4 : STD_LOGIC; 
  signal cntrlr_buf_full6_NE_3 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_5 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_6 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_3 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_4 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_1 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_s_2 : STD_LOGIC; 
  signal cntrlr_N_1074 : STD_LOGIC; 
  signal cntrlr_out_state_10_Q : STD_LOGIC; 
  signal cntrlr_N_853 : STD_LOGIC; 
  signal cntrlr_N_861 : STD_LOGIC; 
  signal cntrlr_N_857 : STD_LOGIC; 
  signal cntrlr_dataen_in : STD_LOGIC; 
  signal cntrlr_sof_in : STD_LOGIC; 
  signal cntrlr_un9_sof_in : STD_LOGIC; 
  signal cntrlr_fsm_state_34_i_and2_0_203 : STD_LOGIC; 
  signal cntrlr_N_872 : STD_LOGIC; 
  signal cntrlr_G_619_146 : STD_LOGIC; 
  signal cntrlr_G_619_144 : STD_LOGIC; 
  signal cntrlr_G_619_141 : STD_LOGIC; 
  signal cntrlr_G_619_140 : STD_LOGIC; 
  signal cntrlr_buf_full : STD_LOGIC; 
  signal cntrlr_un67_char_buf_out : STD_LOGIC; 
  signal cntrlr_out_state_6_Q : STD_LOGIC; 
  signal cntrlr_out_state_7_Q : STD_LOGIC; 
  signal cntrlr_out_state_4_Q : STD_LOGIC; 
  signal cntrlr_out_state_5_Q : STD_LOGIC; 
  signal cntrlr_I_122_i_228 : STD_LOGIC; 
  signal cntrlr_G_619_143 : STD_LOGIC; 
  signal cntrlr_regex_en_0_0_and2_0_207 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_s_8 : STD_LOGIC; 
  signal cntrlr_un1_un1_buf_full6_i : STD_LOGIC; 
  signal cntrlr_out_ptr_lcry_i : STD_LOGIC; 
  signal cntrlr_N_412_i : STD_LOGIC; 
  signal cntrlr_sod_out : STD_LOGIC; 
  signal cntrlr_fifo_we : STD_LOGIC; 
  signal cntrlr_eof_in : STD_LOGIC; 
  signal cntrlr_sod_in : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_6 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_5 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_4 : STD_LOGIC; 
  signal cntrlr_VCC : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_3 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_2 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_1 : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_0 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_7 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_6 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_5 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_4 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_3 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_2 : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_1 : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_7_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_6_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_5_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_4_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_3_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_2_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_1_O : STD_LOGIC; 
  signal cntrlr_input_ptr_cry_0_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_7_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_6_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_5_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_4_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_3_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_2_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_1_O : STD_LOGIC; 
  signal cntrlr_out_ptr_cry_0_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_9_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_8_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_7_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_6_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_5_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_4_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_3_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_2_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_1_O : STD_LOGIC; 
  signal cntrlr_regex_ptr_cry_0_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_6_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_5_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_4_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_3_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_2_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_1_O : STD_LOGIC; 
  signal cntrlr_un1_input_ptr_2_cry_0_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_7_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_6_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_5_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_4_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_3_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_2_O : STD_LOGIC; 
  signal cntrlr_un14_input_ptr_cry_1_O : STD_LOGIC; 
  signal cntrlr_output_fifo_N2147483644 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2147483641 : STD_LOGIC; 
  signal cntrlr_output_fifo_N114 : STD_LOGIC; 
  signal cntrlr_output_fifo_N113 : STD_LOGIC; 
  signal cntrlr_output_fifo_N116 : STD_LOGIC; 
  signal cntrlr_output_fifo_N112 : STD_LOGIC; 
  signal cntrlr_output_fifo_N111 : STD_LOGIC; 
  signal cntrlr_output_fifo_N109 : STD_LOGIC; 
  signal cntrlr_output_fifo_N108 : STD_LOGIC; 
  signal cntrlr_output_fifo_N107 : STD_LOGIC; 
  signal cntrlr_output_fifo_N118 : STD_LOGIC; 
  signal cntrlr_output_fifo_N106 : STD_LOGIC; 
  signal cntrlr_output_fifo_N760 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1078 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1092 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1073 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1108 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1122 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1074 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1138 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1152 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1075 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1168 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1076 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1339 : STD_LOGIC; 
  signal cntrlr_output_fifo_N805 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1415 : STD_LOGIC; 
  signal cntrlr_output_fifo_N804 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1491 : STD_LOGIC; 
  signal cntrlr_output_fifo_N803 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1567 : STD_LOGIC; 
  signal cntrlr_output_fifo_N802 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1636 : STD_LOGIC; 
  signal cntrlr_output_fifo_N764 : STD_LOGIC; 
  signal cntrlr_output_fifo_N845 : STD_LOGIC; 
  signal cntrlr_output_fifo_N855 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1640 : STD_LOGIC; 
  signal cntrlr_output_fifo_N844 : STD_LOGIC; 
  signal cntrlr_output_fifo_N854 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1628 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1633 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1627 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1632 : STD_LOGIC; 
  signal cntrlr_output_fifo_N843 : STD_LOGIC; 
  signal cntrlr_output_fifo_N853 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1626 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1631 : STD_LOGIC; 
  signal cntrlr_output_fifo_N842 : STD_LOGIC; 
  signal cntrlr_output_fifo_N852 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1625 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1630 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1638 : STD_LOGIC; 
  signal cntrlr_output_fifo_full : STD_LOGIC; 
  signal cntrlr_output_fifo_N1907 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1921 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1902 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1937 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1951 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1903 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1967 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1981 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1904 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1997 : STD_LOGIC; 
  signal cntrlr_output_fifo_N1905 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2168 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2244 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2320 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2396 : STD_LOGIC; 
  signal cntrlr_output_fifo_N815 : STD_LOGIC; 
  signal cntrlr_output_fifo_N814 : STD_LOGIC; 
  signal cntrlr_output_fifo_N813 : STD_LOGIC; 
  signal cntrlr_output_fifo_N812 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2563 : STD_LOGIC; 
  signal cntrlr_output_fifo_N820 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2567 : STD_LOGIC; 
  signal cntrlr_output_fifo_N819 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2555 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2560 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2554 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2559 : STD_LOGIC; 
  signal cntrlr_output_fifo_N818 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2553 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2558 : STD_LOGIC; 
  signal cntrlr_output_fifo_N817 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2552 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2557 : STD_LOGIC; 
  signal cntrlr_output_fifo_N2565 : STD_LOGIC; 
  signal cntrlr_output_fifo_BU27_O : STD_LOGIC; 
  signal cntrlr_output_fifo_BU27_LO : STD_LOGIC; 
  signal cntrlr_output_fifo_BU30_O : STD_LOGIC; 
  signal cntrlr_output_fifo_BU30_LO : STD_LOGIC; 
  signal cntrlr_output_fifo_BU42_O : STD_LOGIC; 
  signal cntrlr_output_fifo_BU76_O : STD_LOGIC; 
  signal cntrlr_output_fifo_BU76_LO : STD_LOGIC; 
  signal cntrlr_output_fifo_BU79_O : STD_LOGIC; 
  signal cntrlr_output_fifo_BU79_LO : STD_LOGIC; 
  signal cntrlr_output_fifo_BU91_O : STD_LOGIC; 
  signal cntrlr_output_buffer_N2147483644 : STD_LOGIC; 
  signal cntrlr_output_buffer_N2147483641 : STD_LOGIC; 
  signal cntrlr_regex_buffer_N2147483644 : STD_LOGIC; 
  signal cntrlr_regex_buffer_N2147483641 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_322 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_327 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_338 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_343 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_347 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_352 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_357 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_362 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_365 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_370 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_18 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_16 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_463 : STD_LOGIC; 
  signal cntrlr_match_fifo_mfifo_avail_1 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_324 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_340 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_345 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_349 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_359 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_364 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_367 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_372 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_354 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_490 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_487 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_472 : STD_LOGIC; 
  signal cntrlr_match_fifo_un1_head_1_c1 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_475 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_489 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_468 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_442 : STD_LOGIC; 
  signal cntrlr_match_fifo_wren_buf : STD_LOGIC; 
  signal cntrlr_match_fifo_N_473 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_479 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_460 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_477 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_353 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_344 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_371 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_363 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_351 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_342 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_369 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_361 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_350 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_341 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_368 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_360 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_348 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_339 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_366 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_358 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_329 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_328 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_326 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_325 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_323 : STD_LOGIC; 
  signal cntrlr_match_fifo_un1_rddone_buf_197 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_480 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_467 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_471 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_478 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_476 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_474 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_470 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_469 : STD_LOGIC; 
  signal cntrlr_match_fifo_N_450_i : STD_LOGIC; 
  signal cntrlr_match_fifo_N_448_i : STD_LOGIC; 
  signal cntrlr_match_fifo_N_446_i : STD_LOGIC; 
  signal cntrlr_match_fifo_N_444_i : STD_LOGIC; 
  signal cntrlr_out_state_h_N_1103 : STD_LOGIC; 
  signal cntrlr_out_state_h_N_790_i : STD_LOGIC; 
  signal cntrlr_out_state_h_GND : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU6_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU10_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU14_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU17_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU19_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU21_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU23_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU25_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU28_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU31_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU37_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU40_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU45_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU51_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU55_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU59_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU62_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU64_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU66_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU68_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU70_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU71_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU72_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU73_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU74_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU77_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU80_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU86_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU89_GSR_OR : STD_LOGIC; 
  signal cntrlr_output_fifo_BU94_GSR_OR : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU0_DOA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU34_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU43_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU83_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU92_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU27_SEL_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_fifo_BU76_SEL_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU0_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU1_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU2_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU3_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOA_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOA_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOA_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_output_buffer_BU4_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU0_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU1_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU2_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU3_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOA_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOA_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOA_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_cntrlr_regex_buffer_BU4_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal regex_in : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal regex_in_0 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal regex_in_1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal data_out : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal matched_flop : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_accept_arr_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_fsm_state : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal cntrlr_prev_ptr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cntrlr_match_fifo_tail : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal regular_expression_machine2_state_h_state : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal regular_expression_machine0_state_h_state : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal accepted : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal regular_expression_machine6_state : STD_LOGIC_VECTOR ( 17 downto 16 ); 
  signal regular_expression_machine0_state_d : STD_LOGIC_VECTOR ( 29 downto 29 ); 
  signal regular_expression_machine1_state : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal regular_expression_machine1_nxt_state_47_i_0_and2_1_s : STD_LOGIC_VECTOR ( 20 downto 20 ); 
  signal regular_expression_machine2_state_d : STD_LOGIC_VECTOR ( 27 downto 27 ); 
  signal regular_expression_machine3_nxt_state_31_i_0_0_and2_2_1 : STD_LOGIC_VECTOR ( 12 downto 12 ); 
  signal regular_expression_machine3_state : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal regular_expression_machine4_state : STD_LOGIC_VECTOR ( 19 downto 0 ); 
  signal regular_expression_machine4_nxt_state_39 : STD_LOGIC_VECTOR ( 17 downto 17 ); 
  signal regular_expression_machine6_state_0 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal regular_expression_machine7_state : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cntrlr_regex_ptr : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal cntrlr_input_ptr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_regex_ptr_qxu : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal cntrlr_out_ptr_4 : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_out_ptr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_out_ptr_qxu : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_input_ptr_qxu : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_fsm_state_1 : STD_LOGIC_VECTOR ( 12 downto 1 ); 
  signal cntrlr_regex_ptr_s : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal cntrlr_out_ptr_s : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_input_ptr_s : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_prev_ptr_fast_fast : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal cntrlr_prev_ptr_fast : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cntrlr_regex_in_3_am : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_regex_in_3_bm : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_char_buf_out : STD_LOGIC_VECTOR ( 32 downto 0 ); 
  signal cntrlr_fifo_dout : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_length : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cntrlr_passed_ptr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_prev_ptr_2 : STD_LOGIC_VECTOR ( 10 downto 2 ); 
  signal cntrlr_fifo_din : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal cntrlr_mfifo_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_out_state_i : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal cntrlr_data_in : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal cntrlr_out_buf_out : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal cntrlr_input_ptr_cry : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_out_ptr_cry : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_regex_ptr_cry : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal cntrlr_output_buffer_doa : STD_LOGIC_VECTOR ( 33 downto 33 ); 
  signal cntrlr_regex_buffer_doa : STD_LOGIC_VECTOR ( 33 downto 33 ); 
  signal cntrlr_match_fifo_tail_1 : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal cntrlr_match_fifo_fifo_11 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_7 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_7_am : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_7_bm : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_6 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_4 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_0 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_9_am : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_9_bm : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_12 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_5 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_8 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_10_am : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_10_bm : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_14 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_13 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_10 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_fifo_9 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_am : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_data_out_bm : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_match_fifo_head : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cntrlr_match_fifo_data_buf : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cntrlr_out_state_h_out_state : STD_LOGIC_VECTOR ( 9 downto 9 ); 
begin
  regex_in_2_2_Q_3 : X_BUF
    port map (
      I => regex_in(2),
      O => regex_in_2_2_Q
    );
  regex_in_1_2_Q : X_BUF
    port map (
      I => regex_in(2),
      O => regex_in_1(2)
    );
  regex_in_0_2_Q : X_BUF
    port map (
      I => regex_in(2),
      O => regex_in_0(2)
    );
  regex_in_1_3_Q : X_BUF
    port map (
      I => regex_in(3),
      O => regex_in_1(3)
    );
  regex_in_0_3_Q : X_BUF
    port map (
      I => regex_in(3),
      O => regex_in_0(3)
    );
  regex_in_1_0_Q : X_BUF
    port map (
      I => regex_in(0),
      O => regex_in_1(0)
    );
  regex_in_0_0_Q : X_BUF
    port map (
      I => regex_in(0),
      O => regex_in_0(0)
    );
  regex_in_2_4_Q_4 : X_BUF
    port map (
      I => regex_in(4),
      O => regex_in_2_4_Q
    );
  regex_in_1_4_Q : X_BUF
    port map (
      I => regex_in(4),
      O => regex_in_1(4)
    );
  regex_in_0_4_Q : X_BUF
    port map (
      I => regex_in(4),
      O => regex_in_0(4)
    );
  regex_in_2_1_Q_5 : X_BUF
    port map (
      I => regex_in(1),
      O => regex_in_2_1_Q
    );
  regex_in_1_1_Q : X_BUF
    port map (
      I => regex_in(1),
      O => regex_in_1(1)
    );
  regex_in_0_1_Q : X_BUF
    port map (
      I => regex_in(1),
      O => regex_in_0(1)
    );
  reset_l_2_6 : X_BUF
    port map (
      I => reset_l,
      O => reset_l_2
    );
  reset_l_1_7 : X_BUF
    port map (
      I => reset_l,
      O => reset_l_1
    );
  reset_l_0_8 : X_BUF
    port map (
      I => reset_l,
      O => reset_l_0
    );
  regex_in_2_5_Q_9 : X_BUF
    port map (
      I => regex_in(5),
      O => regex_in_2_5_Q
    );
  regex_in_1_5_Q : X_BUF
    port map (
      I => regex_in(5),
      O => regex_in_1(5)
    );
  regex_in_0_5_Q : X_BUF
    port map (
      I => regex_in(5),
      O => regex_in_0(5)
    );
  d_appl_in_22_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(22),
      O => d_appl_in(22),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_23_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(23),
      O => d_appl_in(23),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_24_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(24),
      O => d_appl_in(24),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_25_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(25),
      O => d_appl_in(25),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_26_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(26),
      O => d_appl_in(26),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_27_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(27),
      O => d_appl_in(27),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_28_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(28),
      O => d_appl_in(28),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_29_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(29),
      O => d_appl_in(29),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_30_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(30),
      O => d_appl_in(30),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_31_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(31),
      O => d_appl_in(31),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_7_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(7),
      O => d_appl_in(7),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_8_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(8),
      O => d_appl_in(8),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_9_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(9),
      O => d_appl_in(9),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_10_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(10),
      O => d_appl_in(10),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_11_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(11),
      O => d_appl_in(11),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_12_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(12),
      O => d_appl_in(12),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_13_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(13),
      O => d_appl_in(13),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_14_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(14),
      O => d_appl_in(14),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_15_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(15),
      O => d_appl_in(15),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_16_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(16),
      O => d_appl_in(16),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_17_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(17),
      O => d_appl_in(17),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_18_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(18),
      O => d_appl_in(18),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_19_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(19),
      O => d_appl_in(19),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_20_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(20),
      O => d_appl_in(20),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_21_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(21),
      O => d_appl_in(21),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_0_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(0),
      O => matched(0),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_1_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(1),
      O => matched(1),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_2_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(2),
      O => matched(2),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_3_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(3),
      O => matched(3),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_4_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(4),
      O => matched(4),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_5_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(5),
      O => matched(5),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_6_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(6),
      O => matched(6),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  matched_7_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => matched_flop(7),
      O => matched(7),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_0_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(0),
      O => d_appl_in(0),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_1_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(1),
      O => d_appl_in(1),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_2_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(2),
      O => d_appl_in(2),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_3_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(3),
      O => d_appl_in(3),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_4_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(4),
      O => d_appl_in(4),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_5_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(5),
      O => d_appl_in(5),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  d_appl_in_6_Q : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => data_out(6),
      O => d_appl_in(6),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  dataen_appl_in_10 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => dataen_out,
      O => dataen_appl_in,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  eof_appl_in_11 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => eof_out,
      O => eof_appl_in,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  sod_appl_in_12 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => sod_out,
      O => sod_appl_in,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  sof_appl_in_13 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => sof_out,
      O => sof_appl_in,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  reset_l_i_8_14 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_8
    );
  reset_l_i_7_15 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_7
    );
  reset_l_i_6_16 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_6
    );
  reset_l_i_5_17 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_5
    );
  reset_l_i_4_18 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_4
    );
  reset_l_i_3_19 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_3
    );
  reset_l_i_2_20 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_2
    );
  reset_l_i_1_21 : X_INV
    port map (
      I => reset_l_0,
      O => reset_l_i_1
    );
  reset_l_i_22 : X_INV
    port map (
      I => reset_l_2,
      O => reset_l_i
    );
  G_723_23 : X_LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      ADR0 => regular_expression_machine5_N_2119,
      ADR1 => regular_expression_machine5_N_2047,
      ADR2 => G_723_sx,
      O => G_723
    );
  G_723_sx_24 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => regular_expression_machine5_N_2099,
      ADR1 => regular_expression_machine5_N_2101,
      ADR2 => regular_expression_machine5_N_2102,
      ADR3 => regular_expression_machine5_N_2083,
      O => G_723_sx
    );
  G_702_25 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(1),
      O => G_702
    );
  G_703_26 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(2),
      O => G_703
    );
  G_704_27 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(3),
      O => G_704
    );
  G_705_28 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(4),
      O => G_705
    );
  G_706_29 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(5),
      O => G_706
    );
  G_707_30 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(6),
      O => G_707
    );
  G_708_31 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(7),
      O => G_708
    );
  G_709_32 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_accept_arr_out(0),
      O => G_709
    );
  G_711_33 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_8_Q,
      ADR1 => cntrlr_out_buf_out_34_Q,
      O => G_711
    );
  G_712 : X_LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      ADR0 => cntrlr_fsm_state(0),
      ADR1 => cntrlr_prev_ptr(1),
      ADR2 => cntrlr_prev_ptr(0),
      O => cntrlr_fifo_we_2
    );
  G_715_34 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => cntrlr_out_state_2_Q,
      ADR1 => cntrlr_out_buf_out_32_Q,
      O => G_715
    );
  G_716_35 : X_LUT3
    generic map(
      INIT => X"14"
    )
    port map (
      ADR0 => cntrlr_match_fifo_un1_rddone_buf,
      ADR1 => cntrlr_match_fifo_tail(0),
      ADR2 => cntrlr_match_fifo_rddone_buf,
      O => G_716
    );
  G_717_36 : X_LUT4
    generic map(
      INIT => X"1444"
    )
    port map (
      ADR0 => cntrlr_match_fifo_un1_rddone_buf,
      ADR1 => cntrlr_match_fifo_tail(1),
      ADR2 => cntrlr_match_fifo_rddone_buf,
      ADR3 => cntrlr_match_fifo_tail(0),
      O => G_717
    );
  G_718_37 : X_LUT3
    generic map(
      INIT => X"14"
    )
    port map (
      ADR0 => cntrlr_match_fifo_un1_rddone_buf,
      ADR1 => cntrlr_match_fifo_un1_tail_19_c2,
      ADR2 => cntrlr_match_fifo_tail(2),
      O => G_718
    );
  G_719_38 : X_LUT4
    generic map(
      INIT => X"1444"
    )
    port map (
      ADR0 => cntrlr_match_fifo_un1_rddone_buf,
      ADR1 => cntrlr_match_fifo_tail(3),
      ADR2 => cntrlr_match_fifo_un1_tail_19_c2,
      ADR3 => cntrlr_match_fifo_tail(2),
      O => G_719
    );
  G_727_39 : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => regular_expression_machine5_N_2085,
      ADR1 => regular_expression_machine5_state_h_state_5_Q,
      ADR2 => reset_l_1,
      ADR3 => regex_en_2,
      O => G_727
    );
  G_730_40 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine2_N_639,
      ADR3 => regular_expression_machine2_state_h_state(1),
      O => G_730
    );
  G_731_41 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine2_N_668,
      ADR3 => regular_expression_machine2_state_h_state(2),
      O => G_731
    );
  G_732_42 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine2_N_696,
      ADR3 => regular_expression_machine2_state_h_state(3),
      O => G_732
    );
  G_733_43 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine2_N_709,
      ADR3 => regular_expression_machine2_state_h_state(4),
      O => G_733
    );
  G_734_44 : X_LUT4
    generic map(
      INIT => X"1504"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine2_N_596,
      ADR3 => regular_expression_machine2_state_h_state(0),
      O => G_734
    );
  G_736_45 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine0_N_688,
      ADR3 => regular_expression_machine0_state_h_state(1),
      O => G_736
    );
  G_737_46 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine0_N_717,
      ADR3 => regular_expression_machine0_state_h_state(2),
      O => G_737
    );
  G_738_47 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine0_N_746,
      ADR3 => regular_expression_machine0_state_h_state(3),
      O => G_738
    );
  G_739_48 : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine0_N_772,
      ADR3 => regular_expression_machine0_state_h_state(4),
      O => G_739
    );
  G_740_49 : X_LUT4
    generic map(
      INIT => X"1504"
    )
    port map (
      ADR0 => regex_restart,
      ADR1 => regex_en_2,
      ADR2 => regular_expression_machine0_N_638,
      ADR3 => regular_expression_machine0_state_h_state(0),
      O => G_740
    );
  N_816_i_50 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => cntrlr_N_811_1_i,
      ADR1 => cntrlr_out_state_0_Q,
      ADR2 => cntrlr_un20_dataen_out_6,
      O => N_816_i
    );
  G_724_2 : X_LUT3
    generic map(
      INIT => X"EA"
    )
    port map (
      ADR0 => regular_expression_machine5_N_2098,
      ADR1 => state_ns_246_0_and2_2_514,
      ADR2 => regular_expression_machine5_N_2215,
      O => N_826_2
    );
  G_724_51 : X_LUT4
    generic map(
      INIT => X"FEEE"
    )
    port map (
      ADR0 => N_826_2,
      ADR1 => regular_expression_machine5_N_2094,
      ADR2 => state_ns_246_0_and2_1_679,
      ADR3 => regular_expression_machine5_N_1470,
      O => G_724
    );
  G_725_1 : X_LUT4
    generic map(
      INIT => X"EAAA"
    )
    port map (
      ADR0 => regular_expression_machine5_N_2092,
      ADR1 => regular_expression_machine5_N_2215,
      ADR2 => regular_expression_machine5_N_2140,
      ADR3 => regular_expression_machine5_N_2126,
      O => N_827_1
    );
  G_725_52 : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => N_827_1,
      ADR1 => regular_expression_machine5_state_h_state_3_Q,
      ADR2 => reset_l_1,
      ADR3 => regex_en_2,
      O => G_725
    );
  G_726_53 : X_LUT4
    generic map(
      INIT => X"FEEE"
    )
    port map (
      ADR0 => regular_expression_machine5_N_2086,
      ADR1 => regular_expression_machine5_N_2087,
      ADR2 => state_ns_322_0_and2_1_678,
      ADR3 => regular_expression_machine5_N_2044,
      O => G_726
    );
  G_710_1 : X_LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      ADR0 => cntrlr_out_state_11_Q,
      ADR1 => cntrlr_fifo_empty,
      O => N_812_1
    );
  G_710_54 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => N_812_1,
      ADR1 => cntrlr_mfifo_avail,
      O => G_710
    );
  G_713_55 : X_LUT4
    generic map(
      INIT => X"3332"
    )
    port map (
      ADR0 => regex_en_0_0_and2_1_226,
      ADR1 => cntrlr_N_1066,
      ADR2 => regex_en_0_0_and2_0_208,
      ADR3 => regex_en_0_0_and2_2_206,
      O => G_713
    );
  regular_expression_machine0_G_88_s_56 : X_LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(4),
      ADR1 => regex_in_0(5),
      ADR2 => regular_expression_machine0_state_h_state(2),
      O => regular_expression_machine0_G_88_s
    );
  regular_expression_machine0_G_109 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => regex_in_2_5_Q,
      ADR1 => regex_in(6),
      ADR2 => regex_in_1(1),
      ADR3 => regular_expression_machine0_G_109_sx,
      O => regular_expression_machine0_N_965
    );
  regular_expression_machine0_G_109_sx_57 : X_LUT4
    generic map(
      INIT => X"FFF7"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(2),
      ADR1 => regular_expression_machine0_state_h_state(4),
      ADR2 => regex_in_0(4),
      ADR3 => regex_in(7),
      O => regular_expression_machine0_G_109_sx
    );
  regular_expression_machine0_G_97 : X_LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      ADR0 => regex_in(6),
      ADR1 => regex_in_1(1),
      ADR2 => regular_expression_machine0_G_97_sx,
      O => regular_expression_machine0_N_953
    );
  regular_expression_machine0_G_97_sx_58 : X_LUT4
    generic map(
      INIT => X"FFFD"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(4),
      ADR1 => regular_expression_machine0_state_h_state(2),
      ADR2 => regex_in_0(4),
      ADR3 => regex_in(7),
      O => regular_expression_machine0_G_97_sx
    );
  regular_expression_machine0_G_90 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => regex_in(7),
      ADR1 => regex_in(6),
      ADR2 => regex_in_2_4_Q,
      ADR3 => regex_in_2_1_Q,
      O => regular_expression_machine0_N_946
    );
  regular_expression_machine0_G_127_bm_59 : X_LUT4
    generic map(
      INIT => X"A0A8"
    )
    port map (
      ADR0 => regular_expression_machine0_G_127_bm_1,
      ADR1 => regular_expression_machine0_N_962,
      ADR2 => regular_expression_machine0_state_h_state(0),
      ADR3 => regex_in_2_5_Q,
      O => regular_expression_machine0_G_127_bm
    );
  regular_expression_machine0_G_127_bm_1_60 : X_LUT4
    generic map(
      INIT => X"4C44"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(0),
      ADR1 => regular_expression_machine0_state_h_state(1),
      ADR2 => regular_expression_machine6_N_308_1,
      ADR3 => regular_expression_machine0_N_947,
      O => regular_expression_machine0_G_127_bm_1
    );
  regular_expression_machine0_G_129 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => regex_in_2_5_Q,
      ADR1 => regular_expression_machine0_N_884,
      O => regular_expression_machine0_N_897
    );
  regular_expression_machine0_G_127 : X_MUX2
    port map (
      IA => regular_expression_machine0_G_127_am,
      IB => regular_expression_machine0_G_127_bm,
      O => regular_expression_machine0_N_895,
      SEL => regular_expression_machine0_state_h_state(3)
    );
  regular_expression_machine0_G_127_am_61 : X_LUT4
    generic map(
      INIT => X"8580"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(0),
      ADR1 => regular_expression_machine0_N_953,
      ADR2 => regular_expression_machine0_state_h_state(1),
      ADR3 => regular_expression_machine0_N_708,
      O => regular_expression_machine0_G_127_am
    );
  regular_expression_machine0_G_116 : X_LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(2),
      ADR1 => regular_expression_machine0_state_h_state(4),
      O => regular_expression_machine0_N_884
    );
  regular_expression_machine0_G_114 : X_LUT4
    generic map(
      INIT => X"E222"
    )
    port map (
      ADR0 => regular_expression_machine0_N_965,
      ADR1 => regular_expression_machine0_state_h_state(1),
      ADR2 => regular_expression_machine0_N_946,
      ADR3 => regular_expression_machine0_N_958,
      O => regular_expression_machine0_N_882
    );
  regular_expression_machine0_G_108 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => regular_expression_machine6_N_308_1,
      ADR1 => regular_expression_machine0_G_88_s,
      ADR2 => regular_expression_machine0_state_h_state(0),
      ADR3 => regular_expression_machine0_state_h_state(1),
      O => regular_expression_machine0_N_964
    );
  regular_expression_machine0_G_106 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => regular_expression_machine6_N_307,
      ADR1 => regex_in_2_1_Q,
      ADR2 => regular_expression_machine0_N_947,
      O => regular_expression_machine0_N_962
    );
  regular_expression_machine0_G_102 : X_LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(2),
      ADR1 => regular_expression_machine0_state_h_state(4),
      O => regular_expression_machine0_N_958
    );
  regular_expression_machine0_G_96 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(1),
      ADR1 => regular_expression_machine0_state_h_state(0),
      O => regular_expression_machine0_N_952
    );
  regular_expression_machine0_G_91 : X_LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(2),
      ADR1 => regular_expression_machine0_state_h_state(4),
      O => regular_expression_machine0_N_947
    );
  regular_expression_machine0_G_89 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => G_1_fast,
      ADR1 => regular_expression_machine0_state_h_state(4),
      ADR2 => regular_expression_machine0_state_h_state(2),
      O => regular_expression_machine0_N_945
    );
  regular_expression_machine0_G_9 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(0),
      ADR1 => regular_expression_machine0_state_h_state(3),
      ADR2 => regular_expression_machine0_state_h_state(1),
      ADR3 => regular_expression_machine0_state_ns_30_s,
      O => regular_expression_machine0_state_d(29)
    );
  regular_expression_machine0_G_87_s_62 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => regex_in_0(5),
      ADR1 => regular_expression_machine0_state_h_state(4),
      O => regular_expression_machine0_G_87_s
    );
  regular_expression_machine0_G_94_s_63 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(2),
      ADR1 => regular_expression_machine0_G_87_s,
      O => regular_expression_machine0_G_94_s
    );
  regular_expression_machine0_accepted : X_SFF
    generic map(
      XON => FALSE
    )
    port map (
      CLK => clk,
      I => regular_expression_machine0_state_d(29),
      O => accepted(0),
      SRST => cntrlr_N_882_1_i_2,
      SSET => accepted(0),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  regular_expression_machine0_state_h_state_ns_180 : X_LUT4
    generic map(
      INIT => X"00FD"
    )
    port map (
      ADR0 => regex_in_1(3),
      ADR1 => regular_expression_machine0_state_h_state(3),
      ADR2 => regular_expression_machine0_state_h_N_710,
      ADR3 => regular_expression_machine0_state_h_state_ns_180_sx,
      O => regular_expression_machine0_state_h_N_744
    );
  regular_expression_machine0_state_h_state_ns_180_sx_64 : X_LUT4
    generic map(
      INIT => X"11B1"
    )
    port map (
      ADR0 => regex_in_1(3),
      ADR1 => regular_expression_machine0_state_h_N_922,
      ADR2 => regular_expression_machine0_state_h_state(3),
      ADR3 => regular_expression_machine0_state_h_N_634,
      O => regular_expression_machine0_state_h_state_ns_180_sx
    );
  regular_expression_machine0_state_h_state_ns_224_i_55_65 : X_LUT4
    generic map(
      INIT => X"A002"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state_ns_224_i_55_1,
      ADR1 => regular_expression_machine0_N_884,
      ADR2 => regex_in_2_5_Q,
      ADR3 => regular_expression_machine0_state_h_state(3),
      O => regular_expression_machine0_state_h_state_ns_224_i_55
    );
  regular_expression_machine0_state_h_state_ns_224_i_55_1_66 : X_LUT4
    generic map(
      INIT => X"6040"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(3),
      ADR1 => regular_expression_machine0_state_h_state(0),
      ADR2 => regular_expression_machine0_state_h_state(1),
      ADR3 => regular_expression_machine0_N_958,
      O => regular_expression_machine0_state_h_state_ns_224_i_55_1
    );
  regular_expression_machine0_state_h_state_ns_57_bm_67 : X_LUT4
    generic map(
      INIT => X"80BE"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state_ns_57_bm_1,
      ADR1 => regular_expression_machine0_state_h_state(0),
      ADR2 => regular_expression_machine0_state_h_state(3),
      ADR3 => regular_expression_machine6_N_308_1,
      O => regular_expression_machine0_state_h_state_ns_57_bm
    );
  regular_expression_machine0_state_h_state_ns_57_bm_1_68 : X_LUT4
    generic map(
      INIT => X"FE32"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(1),
      ADR1 => regular_expression_machine0_state_h_state(3),
      ADR2 => regular_expression_machine0_N_897,
      ADR3 => regular_expression_machine0_state_h_N_624,
      O => regular_expression_machine0_state_h_state_ns_57_bm_1
    );
  regular_expression_machine0_state_h_state_ns_296 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_N_920,
      ADR1 => regular_expression_machine0_state_h_state(0),
      ADR2 => regular_expression_machine0_state_h_state(3),
      ADR3 => regular_expression_machine0_state_h_state(1),
      O => regular_expression_machine0_state_h_N_722
    );
  regular_expression_machine0_state_h_state_ns_68 : X_MUX2
    port map (
      IA => regular_expression_machine0_state_h_N_610,
      IB => regular_expression_machine0_state_h_N_637,
      O => regular_expression_machine0_N_638,
      SEL => regex_in_2_2_Q
    );
  regular_expression_machine0_state_h_state_ns_240_0_and2 : X_LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      ADR0 => regular_expression_machine0_N_920_1,
      ADR1 => regular_expression_machine0_N_947,
      ADR2 => regular_expression_machine7_N_288,
      O => regular_expression_machine0_state_h_N_920
    );
  regular_expression_machine0_state_h_state_ns_240_0_and2_1 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => regex_in_2_1_Q,
      ADR1 => regex_in_2_4_Q,
      O => regular_expression_machine0_N_920_1
    );
  regular_expression_machine0_state_h_state_ns_115_0_and2_0 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(3),
      ADR1 => regular_expression_machine0_N_952,
      ADR2 => regular_expression_machine6_N_308_1,
      ADR3 => regular_expression_machine0_G_88_s,
      O => regular_expression_machine0_state_h_N_922
    );
  regular_expression_machine0_state_h_state_ns_115_0_and2 : X_LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_N_679,
      ADR1 => regular_expression_machine0_state_h_state(0),
      ADR2 => regular_expression_machine0_state_h_state(3),
      O => regular_expression_machine0_state_h_N_921
    );
  regular_expression_machine0_state_h_state_ns_105_0_and2_0 : X_LUT4
    generic map(
      INIT => X"A280"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_state(3),
      ADR1 => regular_expression_machine0_state_h_state(0),
      ADR2 => regular_expression_machine0_state_h_N_671,
      ADR3 => regular_expression_machine0_state_h_N_666,
      O => regular_expression_machine0_state_h_N_919
    );
  regular_expression_machine0_state_h_state_ns_127_0 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_N_827,
      ADR1 => regular_expression_machine0_N_945,
      ADR2 => regular_expression_machine0_state_h_state_ns_127_0_and2_0_619,
      ADR3 => regular_expression_machine0_N_953,
      O => regular_expression_machine0_state_h_N_693
    );
  regular_expression_machine0_state_h_state_ns_316 : X_MUX2
    port map (
      IA => regular_expression_machine0_state_h_state_ns_316_am,
      IB => regular_expression_machine0_state_h_state_ns_316_bm,
      O => regular_expression_machine0_state_h_N_757,
      SEL => regular_expression_machine0_state_h_N_827
    );
  regular_expression_machine0_state_h_state_ns_316_bm_69 : X_LUT4
    generic map(
      INIT => X"7350"
    )
    port map (
      ADR0 => regular_expression_machine6_N_308_1,
      ADR1 => regex_in_2_5_Q,
      ADR2 => regular_expression_machine0_N_884,
      ADR3 => regular_expression_machine0_N_946,
      O => regular_expression_machine0_state_h_state_ns_316_bm
    );
  regular_expression_machine0_state_h_state_ns_316_am_70 : X_LUT3
    generic map(
      INIT => X"57"
    )
    port map (
      ADR0 => regular_expression_machine6_N_308_1,
      ADR1 => regular_expression_machine6_N_307,
      ADR2 => regex_in_2_5_Q,
      O => regular_expression_machine0_state_h_state_ns_316_am
    );
  regular_expression_machine0_state_h_state_ns_216 : X_MUX2
    port map (
      IA => regular_expression_machine0_state_h_state_ns_216_am,
      IB => regular_expression_machine0_state_h_state_ns_216_bm,
      O => regular_expression_machine0_state_h_N_624,
      SEL => regex_in_2_5_Q
    );
  regular_expression_machine0_state_h_state_ns_216_bm_71 : X_LUT4
    generic map(
      INIT => X"3533"
    )
    port map (
      ADR0 => regular_expression_machine6_N_307,
      ADR1 => G_1_fast,
      ADR2 => regular_expression_machine0_state_h_state(1),
      ADR3 => regular_expression_machine0_N_947,
      O => regular_expression_machine0_state_h_state_ns_216_bm
    );
  regular_expression_machine0_state_h_state_ns_216_am_72 : X_LUT4
    generic map(
      INIT => X"5333"
    )
    port map (
      ADR0 => regular_expression_machine6_N_307,
      ADR1 => G_1_fast,
      ADR2 => regular_expression_machine0_N_958,
      ADR3 => regular_expression_machine0_state_h_state(1),
      O => regular_expression_machine0_state_h_state_ns_216_am
    );
  regular_expression_machine0_state_h_state_ns_210 : X_MUX2
    port map (
      IA => regular_expression_machine0_state_h_N_761,
      IB => regular_expression_machine0_state_h_N_771,
      O => regular_expression_machine0_N_772,
      SEL => regex_in_2_2_Q
    );
  regular_expression_machine0_state_h_state_ns_209 : X_MUX2
    port map (
      IA => regular_expression_machine0_state_h_state_ns_209_am,
      IB => regular_expression_machine0_state_h_state_ns_209_bm,
      O => regular_expression_machine0_state_h_N_771,
      SEL => regex_in_1(0)
    );
  regular_expression_machine0_state_h_state_ns_209_bm_73 : X_LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      ADR0 => regex_in_1(3),
      ADR1 => regular_expression_machine0_state_h_N_635,
      ADR2 => regular_expression_machine0_state_h_N_707,
      O => regular_expression_machine0_state_h_state_ns_209_bm
    );
  regular_expression_machine0_state_h_state_ns_209_am_74 : X_LUT4
    generic map(
      INIT => X"444E"
    )
    port map (
      ADR0 => regex_in_1(3),
      ADR1 => regular_expression_machine0_state_h_N_737,
      ADR2 => regular_expression_machine0_state_h_state_ns_224_i_55,
      ADR3 => regular_expression_machine6_N_308_1,
      O => regular_expression_machine0_state_h_state_ns_209_am
    );
  regular_expression_machine0_state_h_state_ns_199 : X_MUX2
    port map (
      IA => regular_expression_machine0_state_h_state_ns_199_am,
      IB => regular_expression_machine0_state_h_state_ns_199_bm,
      O => regular_expression_machine0_state_h_N_761,
      SEL => regex_in_1(0)
    );
  regular_expression_machine0_state_h_state_ns_199_bm_75 : X_LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      ADR0 => regex_in_1(3),
      ADR1 => regular_expression_machine0_state_h_N_759,
      ADR2 => regular_expression_machine0_state_h_N_757,
      O => regular_expression_machine0_state_h_state_ns_199_bm
    );
  regular_expression_machine0_state_h_state_ns_199_am_76 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_N_750_1,
      ADR1 => regular_expression_machine0_state_h_state(3),
      O => regular_expression_machine0_state_h_state_ns_199_am
    );
  regular_expression_machine0_state_h_state_ns_182 : X_LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      ADR0 => regular_expression_machine0_state_h_N_731,
      ADR1 => regular_expression_machine0_state_h_N_745,
      ADR2 => regex_in_2_2_Q,
      O => regular_expression_machine0_N_746
    );
  regular_expression_machine0_state_h_state_ns_181 : X_LUT3
    generic map(
      INIT => X"CA"
    )