| CS/COE 536 | Reconfigurable System on Chip Design | Lockwood, Fall 2002 |
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Part 1 |
| Assigned | Monday, October 7, 2002 at 4:00PM |
| Due Date | Thursday, October 17, 2002 at 5:00PM |
| Description: | Modify the firewall to use 4 CAMs with the new control packet. This is the first checkpoint for verifying that the hardware functions correctly. Plan the two finite
state machines (enqueue and dequeue) |
| Points | 50 |
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Part 2 |
| Assigned | Monday, October 14, 2002 at 4:00PM |
| Due Date | Thursday, October 24, 2002 at 5:00PM |
| Description: | Add packet buffering and priority and per-flow pacing to the firewall. Implement the queue manager that uses a 3DQ scheduler to service flows. The flow contexts must be maintained in SRAM. The queue manager will interface to the flow buffer to supply the head and tail pointers needed for packet read and write operations. |
| Points | 100 |