As the Internet continues to be used for more applications,
computer networks will perform more functions.
In order to implement these new functions at full speed,
much of the data processing operations will be implemented
in hardware. This class will explore the techniques of
migrating networking algorithms from software to hardware.
Machine problems will be implemented that cover
processing and queuing data in Field Programmable Gate Arrays (FPGAs).
Review of Design tools for synthesis and simulation of hardware
Develop a test bench for networking modules
Defining the role of reprogrammable hardware in network routers
Determine the requirements for streaming media applications
Analyze of performance of networking modules for
Queuing and packet processing
Implement Network processing function in hardware (Project)
TEXTBOOKS/READING
Course Textbook
Sudhakar Yalamanchili, VHDL: Starter's Guide: From Simulation to
Synthesis, 2001, ISBN 0-13-080982-9 (In Bookstore)
Select Readings from networking conferences and journals
John W. Lockwood,
Evolvable Internet Hardware Platforms,
NASA/DoD
Workshop on Evolvable Hardware (EHW'01),
Long Beach, CA,
July 12-14, 2001,
pp. 271-279.