Machine Problem 1

Instructions

• Visit the Urbauer 116 Laboratory to perform the exercises described below.
• Show your results to a laboratory assistant.
• Save your results back to the CVS repository.

Part 1: Simulation of the TCP/IP Module in MP1

Using the files provided via CVS in the previous machine problem,
simulate the operation of PortTracker circuit to determine how many flows of occur on a network.

1. In the base directory, run
   make clean

2. If you are in WINDOWS: Source the cygset file to set up your environment:
   source cygset
   If you are in LINUX: Source the simset file to set up your environment:
   source simset

3. Compile the VHDL files:
   make compile

4. Ready the simulation environment:
   make sim

5. Copy the INPUT_CELLS_LC.DAT file from the base directory into the sim directory:
   cp INPUT_CELLS_LC.DAT sim/
   This must be done every time you run a make clean!

6. Change to the sim directory and execute the following command (also listed in the command file in the sim directory):
   vsim -lib work testbench -do "testbench.do" &

7. Wait patiently, as it will take a while to simulate. The simulation will go for 85us.

This tutorial is designed to familiarize you with ModelSim as well as give you a grounding in the operation of a circuit that uses the TCP Processor.

When ModelSim opens it will open three windows. The one we are interested in is the wave window.

Start out by making the wave window as large as you can (this will make things easier). Something to keep in mind as you go along is that if you click on a waveform, it will jump the cursor there to where you clicked and show you the values of the signals at that time in the left column. However, if you are not zoomed in enough, as you move the cursor in the right window (say, by clicking and dragging), the values updated on the left may actually not be consecutive values within the waveform. So if you are not seeing the results you expect, don't forget to zoom in closely and ensure that you aren't simply missing data.

The middle mouse button (the wheel button, or if you have a two-button mouse it may be both buttons together) is an important one -- it allows for easy zooming. Middle-clicking and dragging the mouse down and to either side will allow you to zoom in on a region. Middle-clicking and dragging the mouse up and to the right wil let you zoom out to a specified degree, and middle-clicking and dragging the mouse up and to the left will cause you to zoom out fully (and fit the waveforms in the window).

Look at the signals. For the sake of simplicity, many of the signals within the overall PortTracker application have been removed from the default view. If you wish to add these back in, you can do so by highlighting the desired signals in the singals window, right-clicking on them, and selecting Add. If you add signals or change colors or anything like that and wish to save the waveform view, be sure to click the Save button (the floppy disk icon) and save the file as wave.do in the sim directory.

The signals that you can see in the default view are as follows (the colors are in parentheses):

• PortTracker: The clock signal and some miscellaneous signals (green).

• Port Indicator Signals: The signals that signify that the PortTracker application has detected a packet on one of its watched ports. These signals map out to the ControlProcessor, which actually stores the counts of how many times each port has been seen (magenta).

• Internal Signals: Internal signals within the PortTracker circuit, that map to inputs or outputs. You may wonder why these are listed first, instead of the actual input or output signals. This is because the port detection is actually based upon the internal signals, now the input signals (cyan).

• Input Signals: Signals coming in from other parts of the circuit (yellow).

• Output Signals: Signals going out to other parts of the circuit (dark orchid).

• ControlProcessor: Handles the total port counts and sending out the statistics packets. Note that no signals have been removed from the ControlProcessor in the default wave view (indian red).

First, search for a signal called int_data, which is what the data_in input signal maps to. Do this by going to the Edit menu and selecting Find. Find is good for looking for a specific signal, while Search (underneath Find in the Edit menu) is good for scouring the entire waveforms looking for a value. You may have to click on a signal first before selecting Find, if it complains, and may have to search up or down, depending on which signal you've clicked on. Look for the signal data_in that is part of porttracker_application.

Note how it is showing the data that is being read in from the file (you can verify this by looking at the INPUT_CELLS_LC.DAT file if you wish). Right click on the signal, choose Radix, and select ASCII. Note that you can also select the signal's radix to be binary, octal, etc.

Just above the int_data signal you should see a large number of signals that are mostly staying at a low level. These are the signals that the porttracker_application asserts when it finds a packet with a port of interest.

Just below the int_data signal are several signals that show the status of the incoming packet. sof stands for "Start of Frame" while soip stands for "Start of IP" for IP packets. Note how the int_istcp signal is asserted when the int_sof signal is asserted; this is the TCP Processor's way of saying that this is a valid TCP packet. Note how at about 14.5us, as well as a few other times, the int_sof signal is asserted but the int_istcp signal is not. What do you think this means? (Hint: does the int_soip signal get asserted at these times?)

Questions

• Note how the signals above int_data are asserted. In particular, look for the http signal. to answer the questions below.
  1. What page was visited ?

     http:// _____________________________________________

  2. What browser was being used ?

     _______________________

  3. What web server software was the remote host using ?

     ________________________________________

  You may notice that you can't really read much of the web page, other than the HTTP headers. Look through the data and see if you can figure out why (this is tricky, so don't worry if you can't figure it out...as a hint, however, the answer lies not in the data itself but in the headers).

• Another type of packets in the simulation are SSH packets
  • Why useful information can be obtained from the packet data ?
    Hint: Some parts of a SSH connection are unencrypted?

    _________________________________________________________________

• Another component in the system is the ControlProcessor.
  • Describe the interesting event that occurs around 50 us

    ___________________________________________________________-

Remarks

• By this point, combined with the information about the PortTracker presented in class, you should be on the track to understanding the basics of working with the TCP Proessor. Look at the rest of the simulation. In particular, look at the signal names, which are mostly self-describing.
• Review the porttracker.vhd, porttracker_module.vhd, and control_proc.vhd files and familiarize yourself a bit with the VHDL code for the state machines and processes used in this circuit.
• Feel free to post questions to the bulletin board if you have any.

Part 2: Extend the functionality of PortMapper Module

Requirements

1. Describe the the relationships between structural components found in each of the following three files:
   • porttracker_module.vhd
   • porttracker.vhd
   • control_proc.vhd
   In particular, describe which groups of signals map to which components, and why.

   ____________________________________________________________

   ____________________________________________________________

   ____________________________________________________________

   ____________________________________________________________

2. Build a circuit that detects packets on port 5524 in the same fashion as it detects packets on other ports.
   • Note that the port number, 5524, is given to you in the decimal radix
   • Name the new service that you are detecting "CSE566MP1."

3. Include count statistics for this packet in the statistics packet that the circuit sends out.

4. Use the following, new INPUT_CELLS_LC.DAT to source traffic into your circuit.

5. Modify the wave.do file to include the new signals in the simulation.
   • Make the color of all of the new signals the same but distinct from all other signals in the waveform

6. Run ModelSim to simulate the operation of your circuit. Note that you should generate an image of the relevant waveforms as a part of the project submission.

Hints

• The IP Wrapper will fill in the length and checksum fields (so you don't have to) for the IP packet that contains the UDP packet, but not the UDP packet itself. UDP checksums are optional; they are set to "ignore" by having a value of all zeros. This is acceptable.

• You will only need to modify code in three VHDL files: porttracker_module.vhd, porttracker.vhd, and control_proc.vhd.

• The wave.do file can be modified by hand. However, it can also be modified by changing the signals within ModelSim and clicking the Save button in the wave window.

Submission

• Create a text file called mp1_notes.txt that answers all of questions posed with the input lines ( _____ ) above.
  
  • Call the file mp1_notes.txt and store it in the top-level directory of your MP1 project.
  • Use cvs add mp1_notes.txt to add the file to your project

• Generate an image of the waveform that shows the trace for your new signal. Store the file as mp1_waveform.ps, mp1_waveform.pdf, mp1_waveform.gif, or mp1_waveform.png in your top-level directory of the MP1 project. Be sure to use CVS to check the file into your mp1 project. This will be graded.

• Check in your changes to the VHDL source code and simulation using CVS. Changes should include the modified VHDL code, .do file, and anything else need to simulate the code. Your project will be graded using your files in the CVS repository.
  • Use cvs ci to check in the changes to the CVS repository.

• Using your account on soc.arl.wustl.edu,
  Verify that all of your files have been checked into your project.