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.TH PARBIT V2.00 "02 January 2004 (V2.00)" WashU-ARL WashU-ARL 
.SH NAME
parbit \- generates a partial bitstream file 
.PD
.SH SYNOPSIS
\fBparbit \fIoption original partial [target]
.PD
.\" =========================================================================
.SH DESCRIPTION
\fIparbit\fP will read a configuration bitstream file (\fIoriginal\fP), 
generated by Xilinx tools, and will create a partial bitstream configuration 
file (\fIpartial\fP), defined by the options file (\fIoption\fP). The partial 
reconfigurable area inside the FPGA is defined by the user. Its position
inside the FPGA will be the same as in the original file (\fISlice\fP
\fIMode\fP). When the optional \fItarget\fP file is used, along with 
some new parameters, the location of partial reconfigurable area can be changed.
This is called \fIBlock\fP \fIMode\fP. There is also an \fIIP (Intellectual Property)\fP 
\fIMode\fP, witch it is possible to define a target bitstream different from the 
original one.
.PD
.\" =========================================================================
.SH ARGUMENTS
.TP
.IR \fIoption\fP
Text file containing user options. Each line of this file has the following 
format:

.Y                \fI<OPTION:VALUE>\fP

\fPSee OPTIONS Section.
.TP
.IR \fIoriginal\fP
Bitstream file generated by Xilinx tools. This file contains the 
reconfigurable area that will be extracted by \fIparbit\fP and transformed
in a \fIpartial\fP bitstream file. In the \fISlice Mode\fP the reconfigurable
area will be placed in the same location it was set in the original 
design. In the \fIBlock Mode\fP this area will be the same, but it will be placed
in a different  location. In the \fIIP Mode\fP this area will be placed in a different 
FPGA.

.TP
.IR \fIpartial\fP
Bitstream file generated by \fIparbit\fP, with the reconfigurable area defined
by the user and its designated location. This location is the same one as in the
\fIoriginal\fP file (\fISlice Mode\fP) or a new one (\fIBlock or IP Mode\fP), defined
by user parameters and the \fItarget\fP file.


.TP
.IR \fItarget\fP 
Bitstream file generated by Xilinx tools. It is necessary only in \fIBlock or IP Mode\fP.
This file contains the fixed configuration for the FPGA, plus an empty area 
reserved to receive the reconfigurable area generated by \fIparbit\fP. The 
location of this empty area has to be passed to the tool (\fITargetRow, 
TargetColumn\fP) and must have the same size as the partial reconfigurable area,
defined in the \fIoption\fP file.
.PD
.\" =========================================================================
.SH OPTIONS
Options and values used in \fIoption\fP file:
.TP
.IR FPGA
FPGA type. The available values are: XCV50E, XCV100E, XCV200E, XCV300E,
XCV400E, XCV405E, XCV600E, XCV812E, XCV1000E, XCV1600E, XCV2000E,XCV2600E,
XCV3200E.
.TP
.IR FPGA_TARGET
FPGA Target type. It is used only in \fIIP Mode\fP, to define the FPGA that will receive
the reconfigurable module (IP). The available values are: XCV50E, XCV100E, XCV200E, XCV300E,
XCV400E, XCV405E, XCV600E, XCV812E, XCV1000E, XCV1600E, XCV2000E,XCV2600E,
XCV3200E.
.TP
.IR StartColumn
Start Column of partial reconfigurable area. This value ranges from 1 to the 
maximum available CLB columns in the chosen FPGA. It is used in both modes: 
\fISlice\fP and \fIBlock\fP.
.TP
.IR EndColumn
End Column of partial reconfigurable area. This value ranges from 1 to the 
maximum available CLB columns in the chosen FPGA. It is used in both modes: 
\fISlice\fP and \fIBlock\fP.
.TP
.IR StartRow
Start Row of partial reconfigurable area. This value is used only in \fIBlock\fP 
mode.It defines, in conjunction with \fIEndRow\fP, the height of the partial 
reconfigurable area. In \fISlice Mode\fP this height is equal to the chip height. 
This value ranges from 1 to the maximum rows in the chosen FPGA. 
.TP
.IR EndRow
End Row of partial reconfigurable area. This value is used only in \fIBlock Mode\fP.
It defines, in conjunction with \fIStartRow\fP, the height of the partial 
reconfigurable area. In \fISlice Mode\fP this height is equal to the chip height. 
This value ranges from 1 to the maximum rows in the chosen FPGA. 
.TP
.IR TargetRow
Row of the new position of partial reconfigurable area. This option defines, with 
\fITargetColumn\fP, the upper left corner of the new location of partial 
reconfigurable area inside the FPGA. It ranges from 1 to the maximum rows available 
in the FPGA, provided that it does not override the FPGA area. This option is 
valid only in \fIBlock or IP Mode\fP.
.TP
.IR TargetColumn
CLB Column of the new position of partial reconfigurable area. This option defines, 
with \fITargetRow\fP, the upper left corner of the new location of partial 
reconfigurable area inside the FPGA. It ranges from 1 to the maximum CLB columns 
available in the FPGA, provided that it does not override the FPGA area. This option 
is valid only in \fIBlock or IP Mode\fP.
.TP
.IR Port
Programming port used to reconfigure the FPGA. The values are: \fIJTAG\fP (JTAG 
serial port) or \fISelectMAP\fP (parallel). The default value is \fISelectMAP\fP.
.TP
.IR Shutdown
Start up sequence. Defines how the FPGA works, during reconfiguration.
The values are: \fIYes\fP (performs a shutdown before resuming new 
configuration) or \fINo\fP (the device continues working, during 
reconfiguration). The default value is \fINo\fP.
.TP
.IR Side
Defines one reconfigurable area equal to half FPGA. The values are: \fIRight\fP
(the right side of FPGA) and \fILeft\fP (the left side of FPGA). The tool 
generates the corresponding values for StartColumn and EndColumn automatically.
This option is valid only in \fISlice Mode\fP.
.TP
.IR Header
Defines if the generated bitstream file will contain the original XILINX 
header, plus PARBIT trailer, or not. The values are: \fIYes\fP 
(XILINX Header + PARBIT Trailer) or \fINo\fP (pure bitstream). The default value is \fINo\fP.
.TP
.IR Verbose
Defines what kind of information will appear on the screen, during parbit running.
The value range is from 0 (none) to 4 (maximum).
.PD
.\" =========================================================================
.SH EXAMPLES
To generate a partial reconfigurable area that includes CLB columns 46 and 47,
for VIRTEX XCV1000E FPGA, in slice mode, verbose level 3, with shutdown and JTAG 
programming port:
.PP
.Y "parbit par-slice.opt altled.bit  alt46-47.bit"
.PP
where:
.Y "\fIpar-slice.opt (options text file):"
.PP
.Y FPGA:XCV1000E
.Y StartColumn:46
.Y EndColumn:47
.Y Port:JTAG
.Y ShutDown:Yes
.Y Verbose:3
.PP
.Y "\fIaltled.bit (Xilinx original bitstream file)"
.PP
.Y "\fIalt46-47.bit (partial bitstream file)"
.PP


To generate a partial reconfigurable area that includes CLB columns 12 and 14, 
between rows 3 and 10, for VIRTEX XCV50E FPGA, in block mode, located in columns
44 through 46 and rows 4 to 11, verbose level 2, without shutdown, SelectMAP 
programming port and no headers:
.PP
.Y "parbit par-block.opt altled.bit  alt44-46.bit targ.bit"
.PP
where:
.Y "\fIpar-block.opt (options text file):"
.PP
.Y FPGA:XCV50E
.Y StartColumn:12
.Y EndColumn:14
.Y StartRow:3
.Y EndRow:10
.Y TargetRow:4
.Y TargetColumn:44
.Y Port:SelectMAP
.Y ShutDown:No
.Y Verbose:2
.Y Header:No
.PP
.Y "\fIaltled.bit (Xilinx original bitstream file)"
.PP
.Y "\fIalt44-46.bit (partial bitstream file)"
.PP
.Y "\fItarg.bit (target bitstream file)"
.PD
.\" =========================================================================
.SH COPYRIGHT 
Distributed with permission from Applied Research Laboratory - Washington 
University in St Louis.
.PD
.\" =========================================================================
.SH AUTHORS 
Edson L. Horta  & John W. Lockwood
.PD
.\" =========================================================================
.SH VERSIONS
.ta \w'vx.xxnn'u +\w'fall 1989'u+3n
.PD 0
.IP "V1.00\t13 Aug 2001" \w'\t\t'u
Edson L. Horta
.PD
.IP "V1.01\t18 Feb 2002" \w'\t\t'u
Edson L. Horta
.PD
.IP "V1.02\t16 Dec 2003" \w'\t\t'u
Edson L. Horta
.PD
.IP "V2.00\t02 Jan 2004" \w'\t\t'u
Edson L. Horta
.PD