## File: rad.ucf ## Backend constraints file for RAD FPGA ## (SW side) ## DataIn (Linecard interface, from NID) NET d_sw_nid(0) LOC=B31; NET d_sw_nid(1) LOC=C31; NET d_sw_nid(2) LOC=C32; NET d_sw_nid(3) LOC=D30; NET d_sw_nid(4) LOC=B33; NET d_sw_nid(5) LOC=D32; NET d_sw_nid(6) LOC=A31; NET d_sw_nid(7) LOC=D31; NET d_sw_nid(8) LOC=A33; NET d_sw_nid(9) LOC=C34; NET d_sw_nid(10) LOC=A34; NET d_sw_nid(11) LOC=D34; NET d_sw_nid(12) LOC=B32; NET d_sw_nid(13) LOC=B36; NET d_sw_nid(14) LOC=A35; NET d_sw_nid(15) LOC=D35; NET d_sw_nid(16) LOC=B37; NET d_sw_nid(17) LOC=D33; NET d_sw_nid(18) LOC=A36; NET d_sw_nid(19) LOC=B34; NET d_sw_nid(20) LOC=B35; NET d_sw_nid(21) LOC=D37; NET d_sw_nid(22) LOC=C33; NET d_sw_nid(23) LOC=F37; NET d_sw_nid(24) LOC=G37; NET d_sw_nid(25) LOC=C35; NET d_sw_nid(26) LOC=F36; NET d_sw_nid(27) LOC=E38; NET d_sw_nid(28) LOC=E37; NET d_sw_nid(29) LOC=G36; NET d_sw_nid(30) LOC=D38; NET d_sw_nid(31) LOC=C38; ## DataOut (Linecard interface, from RAD) NET d_sw_rad(0) LOC=B20; NET d_sw_rad(1) LOC=B21; NET d_sw_rad(2) LOC=E22; NET d_sw_rad(3) LOC=A21; NET d_sw_rad(4) LOC=D22; NET d_sw_rad(5) LOC=C22; NET d_sw_rad(6) LOC=D23; NET d_sw_rad(7) LOC=A22; NET d_sw_rad(8) LOC=B22; NET d_sw_rad(9) LOC=E23; NET d_sw_rad(10) LOC=B23; NET d_sw_rad(11) LOC=A23; NET d_sw_rad(12) LOC=C23; NET d_sw_rad(13) LOC=A24; NET d_sw_rad(14) LOC=C24; NET d_sw_rad(15) LOC=B24; NET d_sw_rad(16) LOC=A25; NET d_sw_rad(17) LOC=D26; NET d_sw_rad(18) LOC=B25; NET d_sw_rad(19) LOC=D25; NET d_sw_rad(20) LOC=D24; NET d_sw_rad(21) LOC=C26; NET d_sw_rad(22) LOC=C28; NET d_sw_rad(23) LOC=C25; NET d_sw_rad(24) LOC=B27; NET d_sw_rad(25) LOC=A27; NET d_sw_rad(26) LOC=C27; NET d_sw_rad(27) LOC=A29; NET d_sw_rad(28) LOC=B29; NET d_sw_rad(29) LOC=A28; NET d_sw_rad(30) LOC=B28; NET d_sw_rad(31) LOC=A26; ## Start of Cell NET soc_sw_rad LOC=D27; NET soc_sw_nid LOC=A32; ## TCA NET tcaff_sw_nid LOC=B26; NET tcaff_sw_rad LOC=D39; ## clock NET rad_clk LOC=AW19; ## Reset NET rad_reset LOC=B30;