-- Hello World: Sample FPX Application
-- Operates as Ingress (switch-side) cell processor of RAD
-- Copyright: July 2000, John Lockwood, David Lim
-- Washington University, Applied Research Lab

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- use IEEE.std_logic_unsigned.all;

entity HelloWorld is
	port (rad_clk: in std_logic; -- 100 MHz RAD Clock
		rad_reset: in std_logic; -- Asserted low at startup
		soc_sw_nid: in std_logic; -- Start of Cell [active high]
		tcaff_sw_nid: in std_logic; -- Transmit Cell Available 
		d_sw_nid: in std_logic_vector (31 downto 0); -- Data In
		soc_sw_rad: out std_logic; -- Outgoing Start of Cell
		tcaff_sw_rad: out std_logic; -- [pass through]
		d_sw_rad: out std_logic_vector (31 downto 0) -- Data Out
	);
end HelloWorld;


architecture Hello_arch of HelloWorld is
	type state_type is (rst, dout, hell_check, o_check, world);

        -- "rst": reset state; 
        -- "dout": output of the circuit equal to the input of the circuit; 
        -- "hell_check": checks for the letters "HELL" in the incoming word; 
        -- "o_check": checks for the letter "O"; 
        -- "world": circuit writes out the word "WORLD".

	signal state, nx_state : state_type;
	signal counter, nx_counter : std_logic_vector (3 downto 0);
	signal CEN, nx_CEN : std_logic;

	-- buffer signals to meet timing:
        signal BData_Out : std_logic_vector (31 downto 0);
        signal BData_in  : std_logic_vector (31 downto 0);
        signal BSOC_In   : std_logic;
        signal BTCA_In   : std_logic;
        signal BSOC_Out  : std_logic;
        signal BTCA_Out  : std_logic;
        signal clkin     : std_logic;

begin
   counter_process: process (CEN, counter) begin
	   if CEN = '0' then 
		nx_counter <= "0001";
	   else
	   	nx_counter <= unsigned (counter) + 1;
	   end if;
   end process;

   -- State Transitions
   state_machine_process: process (BSOC_In, state, counter, BData_In, rad_reset, CEN)
   begin
	if ( rad_reset = '1' ) then
	   	nx_state <= rst; 
		nx_CEN <= '0';
	elsif ( BSOC_In = '1' and
		BData_In(19 downto 4) = "0000000000000101" ) then
		-- checks to see if VCI = 5, if so: next check payload
		nx_state <= hell_check;
		nx_CEN <= '1'; 
	elsif ( BSOC_In = '1' and 
		BData_In(19 downto 4) /= "0000000000000101" ) then
                -- VCI != 5
		nx_state <= dout; nx_CEN <= '1';
	elsif ( state = hell_check and counter = "0010" and 
		BData_In="01001000010001010100110001001100" ) then
                -- checks to see if first payload word has letters "HELL"
		nx_state <= o_check;
		nx_CEN <= '1';
	elsif ( state = hell_check and counter = "0010" ) then
                -- Payload[0] != "HELL"
		nx_state <= dout;
		nx_CEN <= '1';
	elsif ( state = o_check and counter = "0011" and 
		BData_In(31 downto 24) = "01001111" ) then
		-- checks to see if second payload word has the letter "O"
		nx_state <= world;
		nx_CEN <= '1';
	elsif ( state = o_check and counter = "0011" ) then
                -- Payload[1] != "O*"
		nx_state <= dout;
		nx_CEN <= '1';
	elsif ( state = world and counter = "0100" ) then
		nx_state <= dout;
		-- Output rest of payload, unchanged.
		nx_CEN <= '1';
	elsif ( state = dout and counter = "1100" ) then
		nx_state <= rst;
		-- Start over for next cell
		nx_CEN <= '0';
	elsif ( state = dout or state = hell_check or state = rst ) then
		nx_state <= state;
		-- same state
		nx_CEN <= CEN;
	else
		nx_state <= state;
		nx_CEN <= 'X';
	end if;
   end process;

   -- Upper 16-bits of Data Output
   DataOut_31downto16_process: process (clkin) begin
	if clkin'event and clkin = '1' then
		-- checks to see if the intput data has the letter "O"...
		if ( state = o_check and BData_In(31 downto 24) ="01001111" ) then
		-- writes out "O " for the higher two bytes of the output
			BData_Out(31 downto 16) <= "0100111101011111"; -- ("O ")
		elsif ( state = world and counter = "0100" ) then
			BData_Out(31 downto 16) <= "0101001001001100"; -- ("RL")
		elsif ( state = rst and BSOC_In /= '1' ) then
			BData_Out(31 downto 16) <= "0000000000000000";
		elsif ( state = dout or state=hell_check or BSOC_In = '1' ) then 
		   	BData_Out(31 downto 16) <= BData_In(31 downto 16);
                else
			BData_Out(31 downto 16) <= "XXXXXXXXXXXXXXXX";
		end if;
	end if;
   end process;

   -- Lower 16-bits of Data Output
   Data_Out_15downto0_process: process (clkin) begin
	if clkin'event and clkin = '1' then
		-- checks to see if the input data has the letter "O"...
		if ( state = o_check and BData_In(31 downto 24) = "01001111" ) then
		-- writes out "WO" for the lower two bytes of the output
			BData_Out(15 downto 0) <= "0101011101001111"; -- ("WO")
		elsif ( state = world and counter = "0100" ) then
			BData_Out(15 downto 0) <= "0100010000101110"; -- ("D.")
		elsif ( state = rst and BSOC_In /= '1' ) then
			BData_Out(15 downto 0) <= "0000000000000000";
		elsif ( state = dout or state=hell_check or BSOC_In = '1' ) then
		   	BData_Out(15 downto 0) <= BData_In(15 downto 0);
		else
		   	BData_Out(15 downto 0) <= "XXXXXXXXXXXXXXXX";
		end if;
	end if;
   end process;

   BData_Out_process: process (clkin) begin
	-- buffer signal assignments:
	if clkin'event and clkin = '1' then
	   d_sw_rad <= BData_Out; -- (Data_Out = d_sw_rad)
	   BData_in <= d_sw_nid; -- (Data_In = d_sw_nid)
           BSOC_In <= soc_sw_nid; -- (SOC_In = soc_sw_nid)
	   BSOC_Out <= BSOC_In;
           soc_sw_rad <= BSOC_Out;  -- (SOC_Out = tcaff_sw_rad)
           BTCA_In <= tcaff_sw_nid; -- (TCA_In = tcaff_sw_nid)
	   BTCA_Out <= BTCA_In;
           tcaff_sw_rad <= BTCA_Out; -- (TCA_Out = tcaff_sw_rad)
           counter <= nx_counter; -- next state assignments
           state <= nx_state; -- next state assignments:
           CEN <= nx_cen;
        end if;
   end process;
  	   	 
   clkin <= rad_clk;
 
end Hello_arch;