Washington University
Saint Louis, MO
August 15-16, 2001
Overview
In this tutorial, you will learn how to accelerate the processing
of packets in reprogrammable hardware using the
Field
Programmable Port Extender. These tutorials will focus on
new applications and tools for the FPX, including the
protocol wrappers, the KCPSM embedded active processor,
the SDRAM Memory controller,
and the NCHARGE control software.
Participants will experiment with hardware/
software co-design through use of the FPX control software.
In the programming laboratory, we will walk through the development
of an actual module using the Xilinx FPGA design tools.
Techniques of processing IP packets in hardware will be demonstrated.
Photos from the Workshop
Agenda
- Wednesday, August 15, 2001
- 8am: Breakfast - 5th Floor Jolley Atrium
- 9am: Session I - Sever 201 Programming Lab
- John Lockwood:
- The FPX Network Platform
- Workshop Objectives & Activities
- Building Networks in Reprogrammable Hardware
- The FPX Network Platform
- Firewall and Router configuration
- Hardware/Software co-design environment
- FPX Architecture:
- Reprogrammable Application Device (RAD)
- Network Interface Device (NID)
- Control and Reconfiguration Tools
- System-On-Chip (SoC) Design Methodology
- Internet Protocol Wrappers
- Applications
- Modular Design on the FPX
- FPX Module Interface
- VHDL Entity
- Control Interface
- Control Processor
- SRAM Memory Interfaces
- SDRAM Memory Interfaces
- Module Design Recommendations
- Edson Horta:
- Todd Sproull: NCHARGE
Control Tools
- NCHARGE Overview
- Features
- Architecture
- Web Interface
- Programming API
- NCHARGE Demo
- Remote SRAM Update
- Remote SDRAM Update
- Control Cell Design Exercise
- Extending NCHARGE with custom software interfaces
- Control Cell Demo
- Lunch - 5th Floor Jolley Atrium
- 1pm: Session II - Sever 201 Programming Lab
- David Lim: Cell Processing in Hardware
- Hardware Compilation Package
- Module Description
- RAD Entity
- VHDL source modifications
- Hardware compiler (vcom)
- ModelSim
- Simulation (vsim)
- Vector changes
- Testbench configuration
- Simulation cell format
- Programming Laboratory Exercises
- Hello and Goodbye World
- Laboratory Exercises
- Synthesis
- cyg_vars
- Hardware Implementation
- Implementation Results
- Sarang Dharmapurikar: A SDRAM memory interface for FPX
- Thursday, August 16, 2001
- 8am: Breakfast - 5th Floor Jolley Atrium
- 9am: Session III - Sever 201 Programming Lab
- Henry Fu : The KCPSM Module
- Lunch - 5th Floor Jolley Atrium
- 1pm: Session IV - Sever 201 Programming Lab
- Henry Fu : Application Development within Wrappers
- Application Brainstorming Session (Open Session)
- Active Network Software Applications
- High-Performance Hardware Applications
More FPX Information
John Lockwood:
lockwood@arl.wustl.edu.