Field Programmable Port Extender:
Spring 2001 Gigabit Workshop Tutorial

Overview

In this tutorial, you will learn how to accerate the processing of packets in reprogrammable hardware using the Field Programmable Port Extender. The tutorial will present the hardware interfaces between the FPX modules and the the infrastructure logic, the SRAM, and SDRAM. Participants will experiment with hardware/ software co-design through use of the FPX control software. In the programming laboratory, we will walk through the development of an actual module using the Xilinx FPGA design tools. Techniques of processing IP packets in hardware will be demonstrated.

Photos from the Workshop

Agenda

• Thursday, January 11, 2001
  • 8am: Breakfast - 5th Floor Jolley Atrium

  • 9am: Session I - Sever 201 Programming Lab
    • John Lockwood: The FPX Environment
    • David Taylor: Modular Design Techniques
    • Todd Sproull: Software Management of an Internet Reprogramable Port Extender.
      • Control Cell software framework
      • FPX Control - Laboratory examples

  • Lunch - 5th Floor Jolley Atrium

  • 1pm: Session II - Sever 201 Programming Lab
    • John Lockwood: Computer Aided Design Tool Environment
      • Software Tool configurations
      • PC Design Environment (Foundation/Synplicity / ModelSimPC / Xilinx backend)
    • Programming the Hello, World Application
      • [Tech Report]: Hello, World: A Simple Application for the Field Programmable Port Extender
        • Module Description
        • Hardware Implementation
        • RAD Entity
        • VHDL Source
        • Implementation Results
      • Simulation of the Hello World Application for the Field Programmable Port Extender (FPX)
        [pdf Talk] and [ppt Talk]
        • Testbench configuration
        • Simulation cell format
        • Laboratory Exercises
          • Simulation vector changes
          • VHDL source modifications
        • Synthesis
      • HelloTestbench.tar: [Complete module and testbench for "Hello, World"]
        • Download and Install these tools as described in handout [above]
    • Sarang Dharmapurikar: A SDRAM memory interface for FPX
      • Using the SDRAM Interface for the FPX
        • SDRAM Interface Description
        • Module Description
        • Timing Diagrams
        • Exercises
      • Steps to compile SDRAM Examples

• Friday, January 12, 2001
  • 8am: Breakfast - 5th Floor Jolley Atrium

  • 9am: Session III - Sever 201 Programming Lab
    • Florian Braun: Higher-level data processing on the FPX
      • The Wrapper Framework
      • Cell Processor
      • Frame Processor
      • IP and UDP Processor
    • Application Example: Hello Bob (ppt /ps /tgz)
      • Application Framework
      • Echo functionality
      • Data flow
      • Use of SRAM for content
      • RAD Core
      • Test bench
      • Simulation
      • Modifications
        • Use of Control cell to modify application VCI
        • Recompilation to modify module ID
        • Detection of checksum errors
        • Recompilation for different port numbers

  • Lunch - 5th Floor Jolley Atrium

  • 1pm: Session IV - Sever 201 Programming Lab
    • David Taylor: Fast IP Lookup Module Tutorial
      • FIPL module design overview
      • FPX file tree navigation
      • Cell I/O simulation exercise (tarfile)
      • Structural VHDL exercise with cell I/O simulation (rad_fipl_shell.vhd)
      • Structural VHDL exercise with cell I/O simulation : Working Solution (rad_fipl_shell_working.vhd)
    • Todd Sproull: Software tools: fipl_mem_mgr and read_fip
      • Extending fpx_control with custom software interfaces
      • fipl_mem_mgr to perform 'Route ADD'
      • read_fip to send cells to FPX_Control
      • FPX_Control to log memory updates
      • Post fpx_control file: NEW_CCP_CELLS.DAT
    • Full IP Router Example
      • Prepend Memory updates to Sample IP Packet Data inputs.
      • Establishing Routes
      • Examine outgoing cells to verify correct forwarding destination.

• FPX Homepage
• FPX-Related References