Unexpected things we've discovered about Cadence

• Leapfrog VHDL Compiler & Simulator
  • The compiler will accept a process that is intended to infer combinational logic, even if the sensitivity list is missing some of the signals that are read inside of the process. Synopsys gives a warning about such missing signals, and infers the desired logic, but Leapfrog happily accepts it with no warnings whatsoever, and then simulates the literal VHDL interpretation of the code, which is to only execute the statements in the process when one of the signals in the sensitivity list changes. This can lead to processes that don't behave like any circuits that I know how to build, and might be impossible to build in circuits.

    I don't know a work-around. One good suggestion is that if you have some code that you want to simulate in Leapfrog, and you intend to synthesize it eventually, then compile it with Leapfrog to verify that it has no syntax errors, then read the VHDL file into Synopsys and look for warnings about signals missing from the sensitivity lists. If there are any, add those signals and recompile under both Leapfrog and Synopsys, in that order. Repeat until no such warnings appear in Synopsys. Note that it is _not_ necessary to synthesize the design in Synopsys to get these warnings. It is only necessary to read in the VHDL file.

  • Manually inserting clock trees in a design is a pain to make it work correctly in the Leapfrog simulator. If you stick in a clock tree of invertors into a parts of a design, but not everywhere, and if all signal assignment statements that are sensitive to a rising edge of clock have no explicit delay in the VHDL code, then you can get an effect that is essentially like a hold violation. (give example).

    The work-around is to put in explicit delays for _all_ signal assignments that happen at a rising edge of clock. Do _not_ put in explicit delays for signal assignments that infer combinational logic, unless you know what you are doing. If you want to make a constant value of type TIME, called tpd for example, and add "after tpd" to all such signal assignments, then define this constant like so:

        -- synopsys synthesis_off
        constant tpd : time := 2 ns;
        -- synopsys synthesis_on
    

    Otherwise, you will get error messages from Synopsys about not being able to handle type TIME. Andy has made an Emacs macro that can make adding such statements to a lot of VHDL code go much faster. (Copy those instructions here).

  • It appears that Leapfrog does not flag errors when declaring two dimensional arrays of signals (i.e., an array of std_logic_vector). However, every time I simulate such code, the two dimensional array always has an undefined value.

    The work-around is just to declare as many separate std_logic_vector's as you need.

    Is this a bug in Leapfrog?

    1998 Sep 30 update: See here for a success story on simulating VHDL with two dimensional array signals in Cadence Leapfrog.

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