The Children of the WUGS

During the course of the design of the Washington University Gigabit Switch, the designers and their spouses had a fair number of children. This web page enumerates them, as well as the designers themselves.

Here are the children, by order of birth.

1994, September 23	Joshua Fingerhut
1995, June 30	Mohsen Hosseini
1995, October 21	Thomas Flucke
1995, December 5	William Chaney (grandchild of the WUGS)
1996, August 5	Keats and Sappho (kittens of the WUGS, who let John DeHart feed them)
1996, September 10	Nikita Parulkar
1996, October 21	Jacqueline Richard
1997, July 21	Owen Fingerhut

And, of course, there are the designers themselves. They are listed in alphabetical order, except for Jonathan Turner, who ought to be first. My deepest apologies if I have left any person out, or have forgotten to acknowledge a significant part of their work -- please correct me!

Jon Turner The original idea man, and inventor of the recycling architecture. Without him, we wouldn't have had all this work to do in the first place!

Tom Chaney Inventor of skew compensation circuit. Physics of electrical circuits, foundry selection and all aspects of interacting with foundry during fabrication and testing, package bonding diagrams, board layouts, physical enclosure design, metastability man, tiny chip design.

Yuhua Chen OPP reformatter.

Hyong-Kyoon (Peter) Chung (my spelling may be off) First versions of IPP virtual circuit translation table, receive buffer, and reformatter.

Ken Cox Switch control software, parts of the specification

John DeHart Switch control software

Zubin Dittia Original System Architecture Document writer and maintainer

Maynard Engebretson Board layout of both versions of main board and all link adaptor boards.

Andy Fingerhut System Architecture Document writer and maintainer, VHDL code for several parts of all three ASIC's, test benches for all ASIC's.

Margaret Flucke Tiny chip, SE cell buffer, OPP resequencer, layout of all three ASIC's. Let me say that again: LAYOUT OF ALL THREE ASIC'S.

Brian Gottlieb Tiny chip, SE input crossbar and grant generation circuit, IPP virtual circuit translation table and receive buffer, Perl programs for all kinds of useful things, Lava Lamp (TM) specialist.

Craig Horn Tiny chip, SE distribution circuit, header modification circuit, output crossbar, and whole chip simulation jockey, both before fabrication and testing first physical parts with hold time violations, IPP reformatter.

Saied Hosseini IPP maintenance register, recycling buffer, and receive circuit, OPP maintenance register and transmit circuit.

Scott Powers Physical enclosure manufacturing diagrams.

William D. Richard All link interfaces, including SUNI 155 Mbps, G-link 1.2 Gbps, dual G-link, dual SUNI 155 Mbps.

Mike Richards Board layout of both versions of main board and all link adaptor boards.

Randy Richards IPP cell store and receive framer, OPP cell store and transmit framer.

Dakang Wu Switch control software

Last updated on November 18, 1997.

andy_fingerhut at-the-machine alum SPOT wustl SPOT edu

Jon Turner	The original idea man, and inventor of the recycling architecture. Without him, we wouldn't have had all this work to do in the first place!
Tom Chaney	Inventor of skew compensation circuit. Physics of electrical circuits, foundry selection and all aspects of interacting with foundry during fabrication and testing, package bonding diagrams, board layouts, physical enclosure design, metastability man, tiny chip design.
Yuhua Chen	OPP reformatter.
Hyong-Kyoon (Peter) Chung (my spelling may be off)	First versions of IPP virtual circuit translation table, receive buffer, and reformatter.
Ken Cox	Switch control software, parts of the specification
John DeHart	Switch control software
Zubin Dittia	Original System Architecture Document writer and maintainer
Maynard Engebretson	Board layout of both versions of main board and all link adaptor boards.
Andy Fingerhut	System Architecture Document writer and maintainer, VHDL code for several parts of all three ASIC's, test benches for all ASIC's.
Margaret Flucke	Tiny chip, SE cell buffer, OPP resequencer, layout of all three ASIC's. Let me say that again: LAYOUT OF ALL THREE ASIC'S.
Brian Gottlieb	Tiny chip, SE input crossbar and grant generation circuit, IPP virtual circuit translation table and receive buffer, Perl programs for all kinds of useful things, Lava Lamp (TM) specialist.
Craig Horn	Tiny chip, SE distribution circuit, header modification circuit, output crossbar, and whole chip simulation jockey, both before fabrication and testing first physical parts with hold time violations, IPP reformatter.
Saied Hosseini	IPP maintenance register, recycling buffer, and receive circuit, OPP maintenance register and transmit circuit.
Scott Powers	Physical enclosure manufacturing diagrams.
William D. Richard	All link interfaces, including SUNI 155 Mbps, G-link 1.2 Gbps, dual G-link, dual SUNI 155 Mbps.
Mike Richards	Board layout of both versions of main board and all link adaptor boards.
Randy Richards	IPP cell store and receive framer, OPP cell store and transmit framer.
Dakang Wu	Switch control software