Calculating the setup and hold times at the pins of a chip

I'm recording this information not because it is difficult to rederive, but because I've derived it at least twice now, and it always takes me about half an hour. Next time I need this information, I'll know where to look it up quickly!

Summary

A positive setup time indicates a time before the active edge of clock, a negative setup time, after.

(setup time at pin of whole chip) =
(setup time of flip-flop data pin)
- (min clock delay from chip pin to FF pin)
+ (max data delay from chip pin to FF pin)

A positive hold time indicates a time after the active edge of clock, a negative hold time, before.

(hold time at pin of whole chip) =
(hold time of flip-flop data pin)
+ (max clock delay from chip pin to FF pin)
- (min data delay from chip pin to FF pin)

Details

Suppose that you have a chip with a data input pin whose signal goes through some delay on chip (e.g., the input pad, RC delay on the wire to a FF (flip-flop) input, some logic inserted expressly for adding delay) before being sampled at a FF. This FF responds to active edges of a clock pin, which is also delayed before it reaches the FF clock input.

Given the setup and hold times of the FF data input relative the the FF clock input, what are the setup and hold times of the pin A relative to the the pin CK of the chip?

Here are some abbreviations used below:

Let's specify the setup-hold window of the FF as follows. The FF will reliably sample the data input as its next state as long as the data input of the FF remains stable in the interval [cf-fsetup, cf+fhold], or:

df is not in [cf-fsetup, cf+fhold]

Alternately:

(df < cf - fsetup) (1)
OR
(df > cf + fhold) (2)

then the FF will reliably sample the data input as its next state. Also suppose that the delay from a transition on the data pin of the whole chip to a transition on the data input of the FF is in the range [dmin, dmax]. Stated another way:

(dc+dmin <= df) (3)
AND
(df <= dc+dmax) (4)

Finally, suppose that the delay from an active transition on the clock pin of the whole chip to an active transition on the clock input of the FF is in the range [cmin, cmax].

(cc+cmin <= cf) (5)
AND
(cf <= cc+cmax) (6)

Now, we wish to determine the smallest interval that the data pin of the whole chip must be stable, of the form [cc-csetup, cc+chold], to guarantee that the FF data pin meets its setup and hold times.

I'm going to derive these "backwards", with a sequence of statements of the form:

statement 1
<== { reason 1 }
statement 2
<==> { reason 2 }
statement 3

This means that statement 2 implies that statement 1 is true, with any justification or comments given as reason 1. It also means that statement 2 is true if and only if statement 3 is true, with any justification given as reason 2.

Here we go, for the setup time:

df < cf - fsetup
<== { (4) }
(dc+dmax) < cf - fsetup
<== { (5) }
(dc+dmax) < (cc+cmin) - fsetup
<==> { algebra }
dc < cc - (fsetup - cmin + dmax)

The final result implies that the setup time at the whole chip is (fsetup - cmin + dmax), as summarized at the beginning.

Now for the hold time, which is derived almost identically:

df > cf + fhold
<== { (3) }
(dc+dmin) > cf + fhold
<== { (6) }
(dc+dmin) > (cc+cmax) + fhold
<==> { algebra }
dc > cc + (fhold + cmax - dmin)

The final result implies that the setup time at the whole chip is (fhold + cmax - dmin), as summarized at the beginning.

Last updated on November 26, 1997.
andy_fingerhut at-the-machine alum SPOT wustl SPOT edu