Before simulating VHDL code behaviorally (we use Cadence Leapfrog VHDL) that is intended to be synthesized eventually, first get it to compile with Cadence Leapfrog (because we have many licenses for that), and then read it into Synopsys (only the Synopsys 'analyze' or 'read' command is necessary, you need not synthesize the design to get the important warning mentioned below) and look for warning and error messages. This can be done with the checksynlog command (source here), like so:
checksynlog log_file_nameFor the purposes of behavioral simulation, probably the most important warning to look for at this point is the one indicating that a signal is missing from a process sensitivity list. This is because it will cause any correct VHDL simulator to simulate that signal's behavior differently than the circuit produced by synthesis. Here is an example:
Warning: Variable 'do_write_cs0' is being read
in routine XMB line 1103 in file '/project/gbn_hw/switch/opp/xmb/temp/a.vhd',
but is not in the process sensitivity list of the block which begins
there. (HDL-179)
It is a good idea to run checksynlog after every run
of dc_shell, to look for things you didn't expect. It is faster than
looking through every line of the log file, so it is more likely that
you'll actually do it, too :-).
pkgaddperm gbn pkgaddperm synopsys pkgaddperm es2_eclp07The 'gbn' package contains the commands waitlicense, checksynlog, and many other useful home-grown scripts.
We only have one floating license for Synopsys, so always use the fastest machine when running dc_shell or design_analyzer. This is currently 'honker', an UltraSparc-2.
If someone else is using the license at the moment (or even if they aren't), and you want to run dc_shell with a script whenever it becomes available, use Rex Hill's 'waitlicense' command (source here), like this:
waitlicense dc_shell -f script_file_name > log_file_nameOr, if you want to save a bit of typing, define the following aliases in your ~/.cshrc.mine file:
alias wdc waitlicense dc_shell -f alias wda waitlicense design_analyzerThen you can type the following instead:
wdc script_file_name > log_file_nameBe careful about using the waitlicense with the design_analyzer command, because the only way to quit design_analyzer is using the GUI at the console where it is being run, or for the owner of the process to kill it. If you run 'waitlicense design_analyzer' and then leave before you get the license, you could grab the license until you return, possibly annoying many others.