library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

package commonDefs is
    constant wordSize: integer := 16;
    constant adrLength: integer := 16;
	 	     
    constant nBtn: integer := 4; -- number of buttons
    constant nSwt: integer := 8; -- number of switches
    constant nLED: integer := 8; -- number of LEDs
    constant nDig: integer := 4; -- number of digits
	 
	 constant operationMode: integer := 1; -- use 0 for simulation, 1 for S3 board
	 constant longDelay: integer := 4+operationMode*100000000; -- 100 million ticks is 2 secs
       
    subtype word is std_logic_vector(wordSize-1 downto 0);
    subtype address is std_logic_vector(adrLength-1 downto 0);
    subtype delayReg is std_logic_vector(27 downto 0);
    
    type regSet is record
        pc: address; iReg: word; acc: word; iar: address;
    end record regSet;
    
    function int(d: std_logic_vector) return integer;
    -- Convert logic vector to integer. Handy for array indexing.
    
end package commonDefs;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

package body commonDefs is
    function int(d: std_logic_vector) return integer is
    -- Convert logic vector to integer. Handy for array indexing. 
    begin return conv_integer(unsigned(d)); end function int;
end package body commonDefs;