Discussion Summary
Paper: Low-Latency Virtual-Channel Routers for On-Chip Networks
Authors: R. Mullins, A. West,
The paper presents the design of a low-latency virtual-channel on-chip network router. Cycle-time and latency are minimized by removing control overhead from the critical path. In general, virtual-channel flow control performs VC allocation and switch allocation in a sequential fashion. By pre-computing arbitration decisions, the authors aim at sparing one clock cycle on each routing operation.
The most part of the reviewers claimed not to have enough knowledge in order to really evaluate the paper. However, there were two categories of concerns: the first one related to the writing style, and the second one on the simulation section.
A big portion of the paper gives background information. The authors mention that the look-ahead concept had already been introduced by Peh and Dally, but do not really compare their solution with the original idea. The real proposal of the paper is presented in a one-page paragraph, and has been considered by several reviewers difficult to follow. In particular, the connection between “requests” and “grant signals” was not immediate to be understood.
The simulation section has been considered poor and not compelling for several reasons:
· Lack of data from real world traffic
· Simulation assumptions not always clearly stated
· Poor comments and fast analysis of simulation results
· Lack of comparison with other routers’ solutions
An initial concern about fair allocation of resources on packets was clarified during the discussion: the proposed scheme seems to be fair.
A general comment was that the paper seems to bring some good ideas, but results not to be really compelling. At the end the reader is not given a clear impression about the validity of the proposed solution.
The ranking varied: few people put the paper in the bottom third, the most in the middle third, and one person in the top third.