The rapid growth in computer communication and multimedia broadband applications is creating an urgent need for high performance and high capacity communication networks. This in turn, drives a need for switching systems that have capacities exceeding 1 terabit per second and with the reliability to operate continuously for long periods of time.
This project will involve the design, development and demonstration of components that will enable construction of ATM switching systems with gigabit link rates and aggregate capacities exceeding 1 Tb/s. A demonstration system with an aggregate capacity of 320 Mb/s will be implemented in this program, with expansion to 1.2 Tb/s requiring only construction of additional copies of I/O and network modules. This project builds upon a highly scaleable ATM switch architecture that exhibits flat cost per port over a very wide range of system configurations, and leverages a substantial technology base of gigabit ATM component technology. The system to be implemented will incorporate the following features:
The figure below shows the overall organization of the Washington University Gigabit Switch (WUGS) architecture.
It consists of three main components, which are each implemented as a single custom integrated circuit. The Input Port Processors (IPP) at left, receive cells from the incoming links, buffer them while awaiting transmission through the central switching network and perform the virtual path/circuit translation required to route cells to their proper output (or outputs). The Output Port Processors resequence cells received from the switching network and queue them while they await transmission on the outgoing link. Each OPP is connected to its corresponding IPP, providing the ability to recycle cells belonging to multicast connections.
The central switching network is made up of Switching Elements (SE) with eight inputs and outputs and a common buffer to resolve local contention. The SEs switch cells to the proper output (or outputs) using information contained in the cell header or can distribute cells dynamically to provide load balancing. The load balancing option is used in the first k-1 stages of a 2k-1 stage network. In particular, for the configuration shown above (k=2), load distribution is performed in the first stage. Adjacent switch elements employ a simple hardware flow control mechanism to regulate the flow of cells between successive stages, eliminating the possibility of cell loss within the switching network. With this approach, relatively small buffers suffice within the network. Larger buffers are provided at the OPPs.
To provide sufficient bandwidth for 2.4 Gb/s data rates on the external links, the switch carries ATM cells in a 36 bit wide format. Four of the 36 bits contain addressing information and the remainder contains the cell payload, together with auxiliary fields that are added by the IPPs and removed by the OPPs. The internal cell cycle is 16 clock ticks long and the clock frequency used is 120 MHz. This yields an internal cell processing rate that is about 1.3 times the cell processing rate for external links operating at 2.4 Gb/s. The switching network is implemented in four parallel planes, with each plane receiving the same four bits of address information, plus eight bits of data. The core of the system operates fully synchronously, and the switch elements' operation is completely deterministic, meaning that the cells proceed through the four planes in parallel, without any explicit coordination, and are reconstructed at the OPP.
Additional stages are added to yield larger configurations. A three stage system can support up to 64 ports and a five stage system, up to 512 ports. Since each port can handle aggregate traffic rates of up to 2.4 Gb/s, system capacities of 1.2 Tb/s can be achieved with 512 ports. The system to be built in this project will have five stages and 128 ports, as shown in the figure below.
The system will be packaged as a set of 64 I/O modules and 64 network cards. Each module contains 8 IPPs, 8 OPPs, two SEs (of four chips each) and the line cards for eight switch ports. Two types of line cards will be implemented. One will be a dual 1.2 Gb/s card (two 1.2 Gb/s interfaces sharing a single ATM switch port) and the other will be a quad 600 Mb/s line card. Each network card implements a portion of the central three stages of one plane of the network.
The central three stages of the interconnection network are the cruicial part of the system from a fault tolerance standpoint, since failures there, have the potential for cutting off all communication. A failure in any single I/O module, on the other hand, affects only the ports that terminate on that I/O module, and in most cases, affects only a single port. Fault tolerance will be achieved by modifying the switch element chip to enable it to route around faulty components in the central part of the network. This will allow the system to continue to operate with reduced overall throughput, in the presence of component failures in the central stages.
Prepared by
Jonathan Turner: jst@cs.wustl.edu
Prepared 7/12/97, Last Modified 7/12/97.