HOMEWORK 6 FAQ (Thu Mar 27, 1425 HOURS)

ERRATA
------
Problem 5, Part c should have this hint:

	HINT:	Use an auxilliary variable to indicate that the value of
		the atomic swap counter is being updated.

Problem 5, Part d should be split into two parts:

	d) Extra Credit -- 2 Points:
                A solution in which the N processes can safely execute a
                sequence of barrier synchronizations must address difficult
	        issues.  Discuss why this is a difficult problem.
	e) Extra Credit -- 2 Points:
		Give a solution in which the N processes can safely execute a
		sequence of barrier synchronizations.  You can use a high-level
		language to describe your solution.

Problem 1
---------

Problem 2
---------

Problem 3
---------
Q3-1)	I know when this algorithm will lead to starvation or livelock, my
	concern is about its mutual exclusion.
	  My question is: Does the algorithm in problem 3 guarantee mutual
	exclusion?   I think it cannot, but the questions in this problem
	seems to be implying that it can, which makes me less confident in my
	answers.
A3-1)	Why do you think that it doesn't guarantee ME?  Can you give me an
	example?

Problem 4
---------
Q4-1)	I think you have an error because the call Wait(X[i-1]) makes no sense
	for i = 0.
A4-1)	If i is 0, process 0 will never execute Wait(X[i-1]).

Q4-2)	I think there is a deadlock in the code.  Consider two processes 0 and
	1.  Process 0 will execute Wait(Y) and block.  Process 1 will then
	execute Wait(X[i-1]) or equivalently Wait(X[0]) and deadlock.
A4-2)	No, the Wait(Y) call will not block.  In general, you should mentally
	organize all semaphores into two groups:  1) ones used to define a
	simple critical section (initial count of 1), and 2) ones with an
	initial count of 0.  Usually, the ones in group 1 are easy to
	understand and the Wait and Signal pairings are physically close
	to each other (not always, but usually).  The complicated signalling
	occurs because of the semaphores in group 2.

Problem 5
---------
Q5-1)	Just to be certain of the syntax, given this program:

		R1 <-- 1;
		R2 <-- 2;
		R1 + R2;
	Is it true that R1 should be 3 and R2 should be 2 still?
A5-1)	Yes, although it would have been clearer if I wrote:

	<operation> ::= <register 1>  <-- <register 1> <bop> <register 2>

Q5-2)	Can we assume process numbers (i.e. each process has a unique variable
	[0-N)) and N are available?
A5-2)	Yes.  But state that.

Q5-3)	Are you looking for an equation using the given assembly code for
	both A and C?
A5-3)	I am looking for the assembler code ... it should be about 10 lines.
	My solution will have both the assembler code and its equivalent
	high-level code description.

Q5-4)	I have an solution for Part a that has only one atomic swap
	instruction ... and it was obvious.  But you make Part c sound
	non-obvious.  I am confused.
A5-4)	It is true that the atomic swap instruction only APPEARS once in
	your solution to Part a.  But you have:

		L1: R1 <---> count
		    ...
		    ... goto L1;
		    ...

	Since it is inside a loop, it may get called/executed many times.

Q5-5)	I don't know how I would put this one into assembly.
	
	int X[N] = {0,...,0}
	process i {
	   X[i] = 1;
	   while ( sum (X) < N ) { /* wait */ }
	   /* critical section */
	}
A5-5)	The right general idea, but ...  Why do you need a global X[] array?
	And the statement after the while is NOT a critical section.
	You want to avoid accessing global, shared data unless you absolutely
	have to for speed.  Why not this:

		int	sum = 0;	// global
		process i {
		    do atomically:  ++sum;
		    while ( sum < N ) { /* wait for last process */ }
		}

	Now, it is straightforward to translate into assembler since:

	o Every arithmetic operation must be done in a register; and
	o To increment Y:

		R0 <-- Y
		incr R0
		R0 --> Y

	o To increment Y atomically you need to acquire a lock; i.e., use
	  "atomic swap" to get a lock ... similar to how TestAndSet is used.

Q5-6)	Verify that they are in order, in the order of their process id. 
	
	int count = 0;
	process i {  /* 0 <= i <= N-1 */
	   int x = i + 1;
	   while ( count < i) { /* wait */ }
	   count <--> x  /* increments count by 1 */
	   while ( count < N-1 ) { /* wait */
	   /* critical section */
	}

	This is not going to work because there is a race condition.  Suppose
	that we are looking at process i = K. The first while-loop becomes
	false when K-1 processes have executed the "count <--> x" statement.
	That means that it possible that processes numbered K+1, ... , N-1
	get to the swap instruction before process K does.  When process N-1
	executes "count <--> x", all proceses waiting in the second while-loop
	will get released prematurely.
	  You could attempt to modify this solution, but maybe you should
	consider something like Q/A5-5 instead.

Q5-7)	I think my solution to Part a solves Parts c&d ... The problem implies
	that this is a difficult problem.  Did I make a mistake?
A5-7)	Your solution is incorrect for both Parts a and c.  You assume that
	every process shares the same register R0. But really, each process
	can be on its own CPU which has its own set of registers.

Problem 6
---------
Q6-1)	I don't understand how Post and Accept should work.
A6-1)	Think of Post and Accept as using a single mailbox.  Post can put
	a value into the mailbox if the mailbox is empty, and Accept can
	get a value from the mailbox if the mailbox is not empty and it is
	the first one in line.  There are two lines:  one for waiting Posts
	and one for waiting Accepts.