• Lecture 1
  • Introduction to CoE/EE 460
  • Introduction to Design Automation
  • Metrics of Logic Synthesis
• Lecture 2
  • Sets and Relations
  • Cartesian Products
  • Karnaugh Maps of 2-5 Variables
  • Relations
• Lecture 3
  • Partial Orders
  • Hasse Diagrams
  • Poset
  • Lattice
• Lecture 4
  • Boole's Expansion Theorem
  • Minterm/Maxterm
  • Pseudo-boolean functions
  • Atoms
• Lecture 5
  • Satisfiability Don't Care
  • Incomplete specification
  • Quine's Prime implicants Theorem
• Lecture 6
  • Techniques of Covering Prime Implicants
  • Unate Covering Problem (UCP)
• Lecture 7
  • Midterm announcement
  • Computational Techniques for logic minimization (1)
    • Representation of logic functions on computers
    • Bit-wise operators on logical values
    • Basic SOP group class
• Lecture 8
  • Reduction techniques for prime implicants
  • Computational Techniques for logic minization (2)
    • Organization of SOP groups
    • Operations on SOP groups
    • Methods to compare groups
    • Organization of groups in Table
    • Extended SOP group class
• Lecture 9
  • Implementation Examples
    • HW3ex.cpp: Sample code for a homework 3 problem
    • Cygwin tools: Freeware (GPL) tools.
    • minterm.exe: Cygwin binary that generates minterms
  • Performance Analysis
• Lecture 10
  • Exam Announcements
  • Maintaining Lists and Groups
  • PI-verbose.exe: Cygwin binary for Verbose Prime Implicant finder
  • Branch and Bound
• Lecture 11
  • Design Flow: Technology independent and dependent phases
  • NMOS / PMOS / CMOS technologies
  • FPGA and LookUp Table (LUT) technologies
• Lecture 12
  • LookUp Table function mapping
  • Decomposition
• Lecture 13
  • Binary Decision Diagrams (BDDs)
    • Support Functions
    • Variable Ordering
    • Creation of a BDD via Boole's Expansion Theorem
    • Reduced BDDs
• Lecture 14
  • Results of Technology-Independent Algorithm Efficiency contest.
• Lecture 15
  • Chortle Algorithm for K-input LUT mapping
    • Dynamic Programming Algorithm
    • Developed by R. Francis, J. Rose, K. Chung, Z. Vranesic (1990s)
    • Calculation of MinMap: Minimum Cost to implement sub-circuit
    • Utilization Division for a subtree
    • Example
• Lecture 16
  • Exam 2 announcement
  • Synthesis of Finite State Machines (FSMs)
    • Synchronous Circuits
    • Next state transitions
    • Outputs of the Mealy and Moore FSMs
    • Informal Synthesis Techniques
    • CLB Mapping of combinatorial logic and state.
• Lecture 17
  • FSM Synthesis Examples
  • Equivalent States
    • K-Equivalent States
    • Partition/Refinement Algorithm for FSM reduction
• Lecture 18
  • Partition/Refinement Algorithm for DFA Reduction
• Lecture 19
  • Final Exam Annoucement
  • Homework 7 and Homework 8 Announcement
  • State Identification
    • Homing Sequences
    • Synchronizing Sequences
    • Distringuishing Sequences
• Lecture 20
  • Finite Automation
  • Regular Languages
  • Accepting States
  • DFA/NFA
  • Final announcements for the semester

Note: These on-line lectures notes serve only as an outline for the material covered in class.
Additional examples and material are covered in class.