CS/COE 535M Fall 2001

Acceleration of Networking Algorithms in Hardware

J. W. Lockwood

ABSTRACT

• As the Internet continues to be used for more applications, computer networks will perform more functions. In order to implement these new functions at full speed, much of the data processing operations will be implemented in hardware. This class will explore the techniques of migrating networking algorithms from software to hardware. Machine problems will be implemented that cover processing and queueing data in Field Programmable Gate Arrays (FPGAs).

INSTRUCTOR

• Prof. John W. Lockwood :
  • Email: lockwood@arl.wustl.edu
    
  • Office Hours: Tue 4pm-5pm
  • Location: Bryan 512 [Enter through Bryan 522]

TEACHING ASSISTANTS

• Teaching Staff
  • David Lim: dlim@arl.wustl.edu
  • Todd Sproull: todd@arl.wustl.edu
  • Sarang Dharmapurikar: sarang@arl.wustl.edu
• Location
  • Bryan 414 / Bryan 416 [Back Hallway]

PREREQUISITE

• Experience with hardware design and VHDL synthesis
  • EE260/CS260M, CoE/EE/CS362, CoE/EE/462 or equivalent
• Experience with computer networks
  • CS423S, CS533M, or equivalent

CLASS FORMAT

• Lecture (once per week)
  • Theory of hardware-based computation
  • Practice of FPGA-based design
• Project Laboratory (once per week)
  • Individual programming assignment (first half of class)
  • Final Project (second half of class)

TIMES & LOCATIONS

• Monday: Programming Laboratory:
  • Time: Monday 4:00pm - 5:30pm
  • Location: Sever 201/202
  • Signup for: Lab A on Mondays
• Wednesday: Classroom
  • Time: Monday 4:00pm - 5:30pm
  • Location: Cupples 1: Room 215
  • Signup for: Lecture Sesion 01 on Wednesdays

WEBSITE

• http://www.arl.wustl.edu/~lockwood/class/cs535/

OUTLINE

• Introduce reprogrammable hardware systems
• Review of Design tools for synthesis and simulation of hardware
• Develop a test bench for networking modules
• Defining the role of reprogrammable hardware in network routers
• Determine the requirements for streaming media applications
• Analyze of performance of networking modules for Queuing and packet processing
• Implement Network processing function in hardware (Project)

TEXTBOOKS/READING

• Select Readings from networking conferences and journals
  • John W. Lockwood, Evolvable Internet Hardware Platforms, NASA/DoD Workshop on Evolvable Hardware (EHW'01), Long Beach, CA, July 12-14, 2001, pp. 271-279.
  • Florian Braun, John Lockwood, Marcel Waldvogel, Layered Protocol Wrappers for Internet Packet Processing in Reconfiguable Hardware, Technical Report WUCS-01-10, Washington University Departement of Computer Science, July 2001.
  • The FPX Wrapper Library homepage, http://www.arl.wustl.edu/arl/projects/fpx/wrappers/, July 2001.
  • Henry Fu and John W. Lockwood, The FPX KCPSM Module: An Embedded, Reconfigurable Active Processing Module for the Field Programmable Port Extender (FPX), Washington University, Department of Computer Science, Technical Report WUCS-01-14, July, 2001.
  • Sarang Dharmapurikar and John Lockwood, Synthesizable Design of a Multi-Module Memory Controller, Washington University, Department of Computer Science, Technical Report WUCS-01-26, October, 2001.
  • John W. Lockwood, Naji Naufel, Jon S. Turner, and David E. Taylor, Reprogrammable Network Packet Processing on the Field Programmable Port Extender (FPX), ACM International Symposium on Field Programmable Gate Arrays (FPGA'2001), Monterey, CA, February 2001, pp. 87-93.
  • John W. Lockwood, Jon S. Turner, David E. Taylor, Field Programmable Port Extender (FPX) for Distributed Routing and Queuing, ACM International Symposium on Field Programmable Gate Arrays (FPGA'2000), Monterey, CA, February 2000, pages 137-144.
  • Sumi Choi, John Dehart, Ralph Keller, John Lockwood, Jonathan Turner and Tilman Wolf; Design of a Flexible Open Platform for High Performance Active Networks, Allerton Conference, Champaign, IL, 1999.
  • S. Hauck, The roles of FPGAs in reprogrammable systems, Proceedings of the IEEE, vol. 86, pp. 615-638, Apr. 1998.
  • RFC 1577: Classical IP and ARP over ATM
  • Austin Donnelly and Tim Deegan, IP Route Lookups as String Matching, IEEELEN'2001, November 9-10, 2001.
  • H. Duan, J. W. Lockwood, S. M. Kang, J. D. Will, A High-performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches, IEEE Infocom '97, Kobe, Japan, April 7-11, 1997, pp 20-28.
  • Donpaul Stephens and Hui Zhang: Implementing Distributed Packet Fair Queuing in a Scalable Switch Architecture, Infocom'98.
  • Anujan Varma, Dimitrios Stiliadis: Hardware Implementation of Fair Queuing Algorithms for Asynchronous Transfer Mode Networks, IEEE Communications Magazine, December 1997, pp. 54-68.
  • Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy, John Wawrzynek, and Andri DeHon, Stream Computations Organized for Reconfigurable Execution (SCORE), Conference on Field Programmable Logic and Applications (FPL), August 28-30, 2000.
• Hardware Synthesis
  • Sudhakar Yalamanchili, VHDL: Starter's Guide: From Simulation to Synthesis, 1999, ISBN 0-13-080982-9 (In Bookstore)
  • Skahill, Kevin: 'VHDL for Programmable Logic', May 1996, ISBN: 0201895730.
  • Rajan, Sundar: 'Essential VHDL: RTL Synthesis Done Right', January 1999, ISBN: 0966959000.

SOFTWARE TOOLS

• ModelSim: Compiler / Simulator
• Synplicity: Hardware Synthesis
• Xilinx Alliance: FPGA Tools
• Cygwin Tools: Freeware GNU Software (g++/gcc)

CREDITS

• 3 units

GRADING

• Homeworks (10%)
  • Submitted to collection box on 2nd Floor hallway in Bryan Hall.
• Machine Problems (30%)
• Midterm (30%)
• Final Project (30%)