Homework Assignment 2

Homework Questions

1. Consider the design of a packet filtering circuit that makes a decision to drop a packet based on a set of rules and the values of several inputs. Given that the circuit has the following entity, design a circuit in three different ways such that all the following rules are enforced.
   • Packet should be dropped if the version has any value except 4 or 6.
   • Packet should be dropped if the the packet has a TTL less than 1.
   • Packet should be dropped if the the Length is more than 1500 bytes.
   • Packet should be dropped if the the protocol is neither TCP or UDP.

   ENTITY packet_filter IS PORT(IS_TCP : in std_logic; -- Packet is of type TCP: ('1'=True, '0'=False) IS_UDP : in std_logic; -- Packet is of type UDP: ('1'=True, '0'=False) VER : in std_logic_vector(3 downto 0); -- Version TTL : in std_logic_vector(7 downto 0); -- Time-To-Live Length : in std_logic_vector(15 downto 0); -- Length (Measured in bytes) Drop : out std_logic); -- '1'=Drop, '0'=Do not Drop END packet_filter;

   1. First, describe the architecture of the circuit using behavioral VHDL without a PROCESS statement.
      Hint: Just think of the circuit a black box with multiple inputs.

      ARCHITECTURE behavioral_1 OF packet_filter IS BEGIN END behavioral_1

   2. Next, describe the same functionality of the circuit using behavioral VHDL with a PROCESS statement.

      ARCHITECTURE behavioral_2 OF packet_filter IS BEGIN drop_process: PROCESS (IS_TCP, IS_UDP, VER, TTL, Length) BEGIN END PROCESS drop_process; END behavioral_2;

   3. Lastly, draw the schematic (diagram) of a structural circuit which implements the same function as above using only COMPARE, AND, OR, and INVERTER components. Draw the inputs as pads on the left, and the output as a pad on the right. You may also use constant-valued signals, as needed. You may assume that the comparator can operate on n-bit numbers and produces multiple logical values to indicate less than, equality, and greater than results.
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
2. The basic FPX entity that will be used to implement the "Hello World" Module is given below:

   entity basic_fpx_module is port(clk : in std_logic; reset_l : in std_logic; soc_mod_in : in std_logic; d_mod_in : in std_logic_vector(31 downto 0); tca_mod_in : in std_logic; soc_out_mod : out std_logic; d_out_mod : out std_logic_vector(31 downto 0); tca_out_mod : out std_logic); end basic_fpx_module;

   1. Write behavioral code for the architecture a module which simply passes cells from input to output.

      architecture behavioral of basic_fpx_module is -- No Signals are needed begin end behavioral

   2. Write behavioral code for the architecture a module which simply passes cells from input to output with a 1 clock-cycle delay.
      Hint: Include a process statement that is sensitive to the clock.
      Hint: Have the compiler infer a Flip/Flop for all signals.

      architecture behavioral of basic_fpx_module is signal soc : std_logic; signal data : std_logic_vector(31 downto 0); signal tca : std_logic; begin end behavioral

   3. Write behavioral code for the architecture a module which only passes cells though the module which are on virtual circuit 5. All other traffic should be dropped.
      Hint: The VCI can be found in 16 bits of the cell header, which is in the first word of the cell's data
      Hint: A cell is dropped if the SOC signal is not asserted.

      architecture behavioral of basic_fpx_module is signal soc : std_logic; signal data : std_logic_vector(31 downto 0); signal tca : std_logic; begin end behavioral