CS/CoE 535 Acceleration of Networking
Algorithms in Hardware 		Lockwood, Fall 2001

Homework Assignment 3

Due: Friday, December 14, 2001, 4pm

Submit to Grader's Box: 2nd Floor of Bryan Hall

75 Points

First Name, Last Name

Homework Questions

Answer the following questions based on the talks and on-line writeups of the CS535 Final projects.
  1. For the traffic generator, what does "IAT" stand for?

  2. For the DRR scheduler, a packet is transmitted when the deficit exceeds what value?

  3. What was the default block size for the optic-flow module?

  4. How many bits per pixel did the optic flow data have after edge detection?

  5. For the SAR module, how many F/Fs were used to implement the fragment buffer?

  6. In the implementation of the tree-based packet classifier, explain what could be specified in a rule.


  7. For the numeric representation project, how many bits were use to represent the mantissa?

  8. For the Fair Queuing Module, how many cell queues could be managed?

  9. For the IDE interface, what pins on the FPX did the project use to interface with the disk?

  10. For the IPv6 Tunneling project, how many tunnels were supported?

  11. For the Video Scaling Project, what factors determine when a packet should be dropped?


  12. For the Motion JPEG Decoder, what did VLC stand for?

Answer the following questions based on the talk and/or published paper describing the SCORE model.
  1. Describe the SCORE model for reconfigurable systems.



  2. What does HSRA stand for?

  3. What aspects of the FPGA does the SCORE model abstract?



  4. What type of graph is used as the abstract model of computation?

  5. What operations can be performed on streams?



  6. What is the FPX equivalent of a stream?