CS/COE 535M Fall 2001

Acceleration of Networking Algorithms in Hardware

J. W. Lockwood

• Lecture 0: The CS/CoE 535 Course

• Lecture 1: Reconfigurable Networking Hardware
  • Course Motivation and Objectives
  • Reconfigurable networking platform
  • Topology of an Internet router
  • Reprogrammable hardware design synthesis cycle

• Lecture 2: Hardware Description Languages
  • Hardware Entities
  • The FPX Network Entity
  • Structural Specification
    • Signals
    • Port Mapping
  • Behavioural Specification
    • Logical and Relational operators
    • Case and conditional clauses
  • Concurrency and the Process Statement

• Lecture 3: Internal Network Data Format
  • Fields of the cell header and payload
  • Problem statement for "Hello, World"
  • Module input/output interface specifications
  • MP1 hardware configuration and simulation testbench

• Lecture 4: Synchronous Machine Design
  • Operation of a clocked process
  • Finite State Machine (FSM) design
  • State declaration, encoding, and transitions
  • Implementation of the FSM in an FPGA
  • MP1 state transitions, hardware structure, and timing diagrams

• Lecture 5: Hardware Compiler, Simulator, and Synthesis Tools
  • Evolvable hardware design cycle
  • Manifest of MP1 files
  • The Cygwin shell
  • Testbench simulation with ModelSim
  • FPGA synthesis with Synplicity
  • Route and Place with Xilinx
  • In-System Demonstation

• Lecture 6: Networking Structures
  • Virtual Circuits and Virtual Paths
  • Adaptation Layers
  • Internet Packet Routing
  • Networking Protocol Stack

• Lecture 7: Layered Internet Protocol Wrappers
  • Layered Hardware Protocol Wrappers
    • Cell Processor
    • Frame Processor
    • IP Packet Processor
    • UDP Packet Processor
  • Timing diagrams and functions of control signals
  • Synthesis and performance results
  • The ROT13 Application

• Lecture 8: Encyption Assignment Details
  • UDP Echo Function
  • Temporal and Spatial Translations
  • Conditional Data Processing
  • MP2 Hardware configuration
    • Devices and switch port configuration
    • FPGA hardware configuration
    • NIC configuration for IP traffic
    • Virutal Circuit Flows
  • Hardware Testing tools (udptestbench)

• Lecture 8s (Supplemental): Protocol Wrapper Notes
  • Using the SOF, SOD, EOF, and DataEn signals
  • Details of the signal timing relationships

• Lecture 9: The KCPSM Module: A Soft-core Processor Module for Active Networking
  • Tradeoffs between Hardware and software packet processing
  • Active Networking
  • Major componets of the KCPSM Module
    • Constant(K) Coded Programmable State Machine (KCPSM)
    • Layered Protocol Wrappers
    • Memory Interface Module
  • Control and Data Packet Types
  • KCPSM Program Template
  • Run Length Encoding (RLE) Example
  • References

• Lecture 10: Simulating the KCPSM Module
  • Assemble and test an active networking program
  • Encapsulate the code into a UDP packet
  • Segment the code packet into cells
  • Download the "Hello" data packet
  • Segment the data packet into a cell
  • Concatenate code and data cells for simulation input
  • Run the 'build' script
  • Remove the 'FPXLib' reference
  • Run the testbench

• Lecture 11: Running the KCPSM Module
  • Interprete results from the KCPSM Module Testbench
  • Select signals to observe
  • Find activity within the waveform
  • Review Memory Map of the KCPSM Module
  • Use NCHARGE to Debug FPX Hardware
    • Generate data
    • Sending aata
    • Receive data
    • Web URL and class login account
  • Interprete results of ChkHello, Rot13, RLE, and RLD
  • Final notes on KCPSM programming
    • Read and write the UDP packet length
    • Use the End-of-String marker
    • In-Place memory processing for RLE.
    • Moving the AAL5 Trailer for RLE and RLD.

• Lecture 12: The FPX SDRAM Memory Interface
  • Implementing rate-controlled packet pacing
  • The FPX optimizing SDRAM controller
  • Performance issues for SDRAM
  • Hardware interface, protocol, and signal timing
  • The cell pacing circuit
  • Implementing FIFOs in Random Access Memory
  • Compilation, simulation, and verification of SDRAM assignment.
  • Effect of adjustment of the pacing and size parameters

• Lecture 13: Hardware/Software Co-Design and Interaction
  • Controlling hardware via the Internet
  • Using Control Cells for message passing
    • Standard Fields
    • User-Defined Fields
  • An on-line, parameterizable queuing module
    • Controlling the Maximum Queue Size
    • Controlling the Pacing Rate
    • Monitoring the current queue size
  • FPX Definition Language.
    • Defining your own opcodes
    • Defining your own communication fields
  • Controlling Modules via the Web
    • Uploading modules
    • Loading modules via the Web
  • Generating your own Testbench
  • Lecture 13s (Supplemental): Hardware Demo

• Lecture 14: Midterm Announcement
  • The CS535 Midterm will be held on Monday, November 19
  • Location: The Couples 1 classroom [Not the lab]
  • Material: Machine Problems, mostly
  • Closed Book, but 2 pages of notes are allowed
  • Solutions

• Lecture 15: Final Projects
  • CS535 Final Project Assignment
  • Project Guidelines: Be modular, be functional, be fast.
  • Instructor and Peer Evaluation
  • Final project Ideas
    • Sequence generator / pattern generator
    • Per-Flow queueing module, WFQ
    • Internet packet filter
    • Memory allocation and garbage collection
    • Genetic sequence matching
    • Data encryption
    • Multimedia processsing (Video, Image, Voice)
    • Scheduling
    • Ninos Kit
    • Something totally different
  • On-line Project Signup
    • Create a project
    • Browse the projects
    • Sample peer evaluation forms
  • Project Writeup
    • Major sections
    • Format
  • Important dates and deadlines

• Lecture 16: Final Course Lecture
  • Final Lecture of the semester
  • MP5 Extension
  • Midterm Exam Reminder
  • Final Project Template (PPT file)
    • [Right-click then 'Save Target As' to use this as your template]
    • Note: The macros are safe and are only used to define special math characters.

• Lecture 17: Upcoming Deadlines
  • Upcoming deadlines
  • Upcoming colloquium on reconfigurable systems
  • DAC student design contest
  • Final project evaluation page sample
  • Midterm Exam Reminder

• Lecture 18: Final Course Lecture
  • Complete Status Reports
  • Review Midterm Solutions
  • Discuss Final Project Talks and Submissions Guidelines
  • Review Lab configuration and Virtual Circuit allocation.
  • Sign up for Project time slots
  • Reminder: Final Class on Wednesday will be in Bryan 509c: 4pm-7pm.