Machine Problem 2

ROT13 Encryption / Decryption in Reprogrammable Hardware

Assigned	Monday September 24, 2001
Due Date	Part 1: Friday, September 28, 2001, 5pm Part 2: Thursday, October 4, 2001, 4pm
Purpose:	Packet processing with the Layered Protocol Wrappers
Points	50

Introduction

The FPX provides simple and fast mechanisms to process cells or packets directly in hardware. By performing all computations in FPGA hardware, cells and packets can be processing at the full line speed of the card [currently 2.4 Gbits/sec].

However, the user may not always want to handle data directly on the cell level. For this assignment, you will use the Layered Protocol Wrappers to implement an encryption/decryption module for UDP datagrams. This circuit will be implemented as a module on the FPX. It instantiates the Layered Protocol Wrappers, which takes ATM Cells from the RAD and implements the ROT13 application with UDP control signals and UDP payload, and instantiates the ROT13 application which encrypt/decrypt the string stored in the UDP payload using the ROT13 algorithm.

Background: Layered Protocol Wrappers

The Layered Protocol Wrappers are used to streamline and simplify the networking functions to process ATM cells, AAL5 frames, IP packets and UDP datagrams directly in hardware. It is a layered design and consists of different processing circuits in each layer. The block diagram of the Layered Protocol Wrappers is shown in Figure 1. At the lowest level, the Cell Processor processes raw ATM cells between network interfaces. At the higher levels, the Frame Processor processes variable length AAL5 frames while the IP Processor processes IP packets. At the user level, the UDP Processor transmits and receives UDP messages. Different layers of abstraction are important for networks because they allow application to be implemented at a level where important details are exposed and irrelevant details are hidden. This way, an application that interacts with IP packets or an application that interacts with UDP messages can equally use the Layered Protocol Wrappers effectively.

Figure 1: Block Diagram of the Layered Protocol Wrappers

Background: The UDP Wrapper

Each circuit in the Layered Protocol Wrappers can be used separately. Also, multiple circuits can be connected together to form a high level wrapper. For example, the Frame Wrapper is formed by connecting the Cell Processor and the Frame Processor together; the IP Wrapper is formed by connecting the Frame Wrapper and the IP Processor together; and the UDP Wrapper is formed by connecting the IP Wrapper and the UDP Processor together. For this assignment, the UDP Wrapper will be used to encapsulate the data sent and received between the RAD and the ROT13 application. The block diagram of the application module is shown in Figure 2.

Figure 2: Block Diagram of the Application Module

Description of the Assignment

The purpose of the first part of this assignment is to instantiate the UDP Wrapper and the ROT13 application and connect them together. The purpose of the second part of this assignment is to actually implement the ROT13 application.

The tar files for this package can be downloaded here. It consists of four folders, sim, syn, vhdl and wrappers. The sim folder includes all the simulation files for use with Modelsim, and the setup is exactly the same as MP1. The syn folder includes the project files for use with Synplicity Pro. The wrappers folder includes all the files from the Layered Protocol Wrappers package. The vhdl folder includes the vhdl files of the ROT13 module. The contents of the tar file is listed below:

ROT13/sim/ Simulation Folder

testbench.vhd The testbench for this FPX module. It is not synthesizable.
clock.vhd The clock for this FPX module. It is not synthesizable.
fake_NID_in.vhd and fake_NID_out.vhd The fake input / output from the NID. It is not synthesizable.
INPUT_CELLS.DAT The input files read by the testbench. Modify this file so that the desired data input is being injected into the RAD.
SW_CELLSOUT.DAT The output files from the egress. Because the loopback_module is instantiated at the egress, the output data is the same as the input data from the NID.
LC_CELLSOUT.DAT The output files from the ingress. Because the ROT13_module is instantiated at the ingress, the output data is modified by the ROT13_module. Look at this file to check if the ROT13_module is actually encrypting or decrypting the data.
testbench.do The Modelsim macro files.
modelsim.ini The Modelsim configuration files. It includes the path to the Xilinx libraries.

ROT13/syn/ Synthesis Folder

proj.prj and proj.prd The project files for Synplicity Pro. It tells Synplicity Pro which vhdl files should be included for synthesis.
rad-xcve1000/ All the synthesis output files should be stored in this folder.
rad-xcve1000/build The backend script for executing the Xilinx backend tools.
rad-xcve1000/rad_loopback.ucf The FPGA chip pin constraints file.
rad-xcve1000/bitgen.ut The BITGEN option file.

ROT13/vhdl/ VHDL Source Folder

blink.vhd The vhdl file for the blink component. It controls the blinking of the LED on the FPX board. There is no need to modify this file.
loopback_module.vhd The vhdl file for the loopback_module that is going to be instantiated by the rad_loopback_core. There is no need to modify this file.
rad_loopback_core.vhd The vhdl file for the rad_loopback_core component. It instantiates the ROT13_module at the ingress and the loopback_module at the egress. There is no need to modify this file.
rad_loopback.vhd The vhdl file for the top-level design of the rad_loopback. There is no need to modify this file.
rot13_module.vhd The vhdl file for the ROT13_module. Modify this file to instantiate the UDPWrapper and the ROT13_app.
rot13_app.vhd The vhdl file for the ROT13_app. Modify this file to instantiate the UDPEcho and ROT13.
udpecho.vhd The vhdl file for the UDPEcho. Modify this file to implement the UDPEcho entity.
rot13.vhd The vhdl file for the ROT13. Modify this file to implement the ROT13 entity.

ROT13/wrappers/ The Layered Protocol Wrappers Package Folder

cellproc_sim.vhd The vhdl file for simulating the Cell Processor. It is not synthesizable.
frameproc_sim.vhd The vhdl file for simulating the Frame Processor. It is not synthesizable.
ipproc_sim.vhd The vhdl file for simulating the IP Processor. It is not synthesizable.
udpproc_sim.vhd The vhdl file for simulating the UDP Processor. It is not synthesizable.
framewrapper.vhdl The vhdl file for the Frame Wrapper. It instantiates the Cell Processor and the Frame Processor and connects them together.
ipwrapper.vhdl The vhdl file for the IP Wrapper. It instantiates the Frame Wrapper and the IP Processor and connects them together.
udpwrapper.vhdl The vhdl file for the UDP Wrapper. It instantiates the IP Wrapper and the UDP Processor and connects them together.
*.edn The EDIF Macro files for synthesis with the Xilinx backend tools.

Part 1: Instantiation of the UDP Wrapper and the ROT13 Application

In this part of the assignment, instantiate the UDP Wrapper and the ROT13 Application in a FPX module inside the RAD. The setup of this module is very similar to the HelloWorld module in MP1. The rad_loopback instantiates the ROT13_module at the ingress and the loopback_module at the egress. The ROT13_module then instantiates the udpwrapper and the ROT13_app.

Modify rot13_module.vhd and make the necessary changes so that it instantiates the UDP Wrapper and the ROT13 application and connects them together. Figure 3, 4, 5 shows the input/output signals of the RAD, the UDP Wrapper and the ROT13 Application.

Figure 3: Input / Output Signals of the RAD

Figure 4: Input / Output Signals of the UDP Wrapper

Figure 5: Input / Output Signals of the ROT13 Application

Part 2: Implementation of ROT13 Application

In this part of the assignment, implement the details of the ROT13 Application. The rot13_app instantiates the UDPEcho and the rot13.

Modify rot13_app.vhd and make the necessary changes so that it instantiates the UDPEcho and the ROT13 and connects them together. Figure 6 and 7 shows the input/output signals of the UDPEcho and the ROT13.

Figure 6: Input / Output Signals of the UDPEcho

Figure 7: Input / Output Signals of the ROT13

Modify udpecho.vhd and make the necessary changes so that it swaps the source and destination IP Address and swaps the source and destination UDP Port.

Modify rot13.vhd and make the necessary changes so that it encrypts or decrypts the string stored in the UDP payload using the ROT13 algorithm. The ROT13 algorithm "rotates" each character in the string by 13 characters. 'A' maps to 'N'; 'M' maps to 'Z'; 'a' maps to 'n'; and 'm' maps to 'z', and so on. Since it rotates each character by 13 and there are 26 characters in the English alphabet, applying the string with the ROT13 algorithm once encrypts the data and doing it again decrypts the data. For example, "Hello" maps to "Uryyb", and "Uryyb" maps to "Hello".

Implementation Hints for UDPEcho and ROT13

Both of the implementation of UDPEcho and ROT13 is similar. Each component should have a finite state machine. In each state, the finite state machine checks the input UDP control signals (DataEn, SOF, EOF, SOD, TCA) to see what the content of the data is (ATM Header, IP Header, UDP Header, UDP Payload, Padding, ATM Trailer, Don't Care). Once the finite state machine knows what the content of the data is, then it can modify the contents of the data. Refers to Figure 8 to understand the header format of a UDP Datagram, and refers to Figure 9 to understand the behavior of the control signals for a UDP Datagram.

Figure 8: Format of a UDP Datagram

Figure 9: Timing Diagram of a UDP Datagram at the Application Level

Also, there is two different implementation for the ROT13. Notice that each character is only 8-bits, but the data bus is 32-bits, so the ROT13 Application needs to process four characters at a time. The ROT13 Application either instantiates one ROT13 entity with a 32-bit data bus or instantiates four ROT13 entities with a 8-bit data bus. Either implementation will do, and it's just a design decision.

Things to Turn In

Here is a check list of the things you need to turn in:

Part 1: Instantiate logic
- Turn in the rot13_module.vhd program. Be sure to compile the code and verify that the syntax is correct.
- Submit Bubble diagram for the state machine of UDPEcho and ROT13.
- Submit VHDL code that performs the rot13 function for a byte-size character.
Part 2: The ROT13 Encryption / Decryption in Reprogrammable Hardware
- Complete VHDL source code that compiles and works.
- Timing diagram(s) (from Modelsim) clearly showing that the module is working correctly.
- PAR Log (rad_loopback.par) identifying signals names and chip utilization and TRCE LOG (rad_loopback.twr) identifying critical path and max frequency.

Please print the grade sheet and staple it on top of your machine problem.