Machine Problem 4

Introduction

There are many ways in which packets can be buffered. The simpliest of all is First-In-First-Out (FIFO). In this machine problem you are to use SDRAM to build a simple FIFO packet buffer for the FPX. The module will accept cells at the input, store them into the FIFO memory, then transmit them to the output in the same order in which they arrived.

The rate at which packets will be transmitted on the outgoing link will be regulated. In this machine problem, we will also implement a control policy which transmits packets no faster than a constant rate.

Description of the Assignment

Rate Control Mechanism

Thus, the module stores incoming cells in the cell FIFO as they arrive and pulls out the cells only at a regular interval. The following diagram shows how the module should be built. Most of the components in this figure are provided to you. You are required to design only the "CellFifo" component in this design.

Components of the Fifo

• GetCell : This is a state machine. Upon receiving a SOC_in, it gets the complete cell in 32 bits at a time and stores it in temporay registers which are 64 bit wide. Thus it receives the 14 words cell on 32 bit interface and formats it into a 7 word cell with 64 bit words.
• PushCell: This is a state machine. Once an input cell is completely assembled into the temporary registers, it pushes the cell into the CellFIFO, 64 bits at a time. First this state machine makes a request to the CellFIFO module to push the cell and waits for the grant. The request is kept high until a grant is received.Once the grant is received, the Push state machine pushes the cell into the CellFIFO.
• Cell FIFO : This is a component you are required to design. It accepts a write request. Then it makes a request to the SDRAM controller to perform a cell write operation. After getting the appropriate grants from the controller, it gives a write grant to the outside entity for pushing the cell in. As the Cell words are pushed in, it writes those words into the SDRAM.

  Likewise, it should accept a read request on the output side, read the cell from the SDRAM and pass it out 64 bits at a time. Since it acts as a Cell FIFO, the incoming cells need to be buffered as a FIFO i.e. the first cell entered should be given out when a read request is made to the CellFifo.

  the CellFifo module has to maintain a CellWritePointer and CellreadPointer.The following diagram illustrates how a simple FIFO looks like. The CellReadPointer points to the next cell in the row when a cell is dequeued. The write pointer points to the next free cell location when a cell is written into the FIFO.
  
  

  
  
  Fifo Pointers

• PullCell : This is a state machine which pulls a cell out of the FIFO. Then it waits for a grant from the Cell FIFO and upon receiving the grant it starts getting the data from the Cell FIFO 64 bits at a time and puts it in the temporay storage. It is just the read counterpart of the PullCell state machine described above.
• SendCell : This is a state machine which sends the cell on the output interface of the module. It reads the cell stored in the temporary registers by the PullCell and sends it on the module output 32 bits at a time. It is the Pull counterpart of the PushCell state machine described above.

Some more clarification for the CellFIFO

• The CellFIFO buffers 'Cells' (14 words, each word 32 bit) in a FIFO fashion
• The FIFO should have the following entity structure




CellFifo Entity
• It maintains a WriteCellPointer and ReadCellPointer
• When there are no cells in the FIFO, both Write and Read Cell pointers point to 0
• The WriteCellPointer always points to an address where a cell can be written
• The ReadCellPointer always points to an address from where a cell can be read
• The read cell pointer points to the next cell in the FIFO when a cell is read out
• The write cell pointer points to the beginning of the next empty cell when a cell is written into the FIFO
• The FIFO stops accepting cells when it is full.
• The FIFO stops giving out cells when it is empty
• It maintains a count of the cells present in the FIFO and gives it out on the 'CellCount'
• If the FIFO gets a read request and the write request at the same time then it should give preference to the read request
• It should adhere to the following timing diagram for Write and Read interface




Waveform on the write interface







Waveform on the read interface

Details of the SDRAM Memory Controller Interface

• Simplifies the user's interface to memory.
• Optimizes memory throughput
• Allows SDRAM to shared by multiple user modules by implementing arbitration functions.
• Enables a user module to make multiple memory requests
• Maintains a strict ordering of memory operations for each individual module.

Connection of a module to the SDRAM controller

The SDRAM Controller interface document gives the details of each signal in the SDRAM controller and shows how to connect a module to the SDRAM controller. This document also describes the protocol for reading and writing the words in the SDRAM. This document should be thoroughly understood before the SDRAM controller is used.

The following figures shows the bubble diagram of a state machine which reads and writes memory. The statements in blue color show the actions to be taken on that clock edge for the Read operation and the statements in the red color show the corresponding actions in a write operation. By default the state-machine sits in the Start state. When the state-machine gets the StartRead or a StartWrite signal, it goes to a Request state and while making this transition, it makes a request by asserting the request signal high for only one clock cycle. The request signal should be pulled down on the next clock edge. From the Request state, the state-machine goes to the WaitGrant1 state where it waits for Grant1 from the SDRAM controller.

Note that the state-machine looks at the Clocked Grant1 signal and not the Grant1 signal. The Grant1 signal must be clocked before it is used

Bubble diagram for state machine that reads and writes to the SDRAM controller

After receiving the ClockedGrant1, the state-machine goes into the SendAddress state and during this transition, it puts the starting address of the burst read/write on the InfoBus. From the SendAddress state, the state-machine goes to the SendBLType state and during this transition it puts the Burst Length and the Operation Type on the InfoBus (as described in the interface document). From the SendBlType state, state-machine goes into the WaitGrant2 state where it keeps waiting for Grant2. Again note that the state-machine looks at the Clocked Grant2 signal and not the Grant2 signal. The Grant2 signal must be clocked before it is used Once the Clocked Grant2 is received, the state-machine goes to the Read/Write state. During this transition it reads or writes the first word. After going to the Read/Write state,it keeps reading or writing the words for the rest of the burst. Once the last word is read or written, the state-machine goes back to the Start state again.

Assignment Details

• Download the tar file here and untar it
• Enhance the generic read/write bubble diagram given above for for the CellFIFO. The bubble diagram should clearly indicate the transitions on all the entity inputs and outputs
• Using your bubble diagram, write the architecture for the 'CellFIFO.vhd' in the vhdl directory. This architecture should use a constant called 'c_MaxCellCount' defined in the PkgPacer.vhd. This constant specifies the size of the FIFO in terms of the maximum number of cells it can accomodate. You are free to modify the value of this constant and define your own size of the FIFO.
• Examine the file TESTCELL.DAT in the sim directoy which has the cells to be pumped into the FIFO intermittantly. The wait statements this file specify the delay between the cells bursts. You are free to modify this file and create your own input cell pattern.
• In the PkgPacer.vhd, a constant called c_PaceInterval defines the rate, in terms of number of clock cycles, at which the cells are pulled out of the CellFIFO. You are free to modify this parameter.
• Compile the architecture with the testbench in the sim directory by running 'make compile'
• Run the simulation in the sim directory by running 'make sim' and pull up the appropriate waveforms
• Demonstrate that:
  • When a bursty patters of cells is pushed into the FIFO, a regularly paced patters of cells will come out of it
  • When the Cell FIFO is full, no more input cells are accepted
  • When the Cell FIFO is empty, no cells come out even if read requests are made

Things to turn in

• Enhanced Bubble diagram, showing all possible transitions for signals
• VHDL code for "CellFIFO"
• Waveforms of the simulation demonstrating all the points mentioned above

Please print the grade sheet and staple it on top of your machine problem.