Edge Filter Module
- Interface
- Input: UDP Packet using signals from protocol wrappers, payload
contains 8bpp of greyscale image data
- Output: UDP Packet using signals from protocol wrappers,
payload contains 1bpp of thresholded image edge data
- Design Subcomponents
- Input_director: A 2*Width
+ 8 byte shift register which shifts 4 bytes of new data for each clock that
the input column is increased. Outputs 12 grayscale pixel values (bytes) from
the 4 subesquent columns in three subsequent rows. The output row is
the index of the center outputted row and the output column is the index
of the 4 outputted columns (size=Width
/4). Output for the first and last rows is duplicated from the second
and the second to last rows (respectively).
- Pixelfilter: First part of filter mask(s).
The input is 3 grayscale pixel values (bytes) from the same column in the
image, on three subsequent rows. The output is the column passed through
each each column of the mask. For each column in the mask, there is
an output integer field. There are actually 2 masks, one to check for
a horizontal edge and one to check for a vertical edge. The horizontal
mask outputs 3 integers (the input passed through the left, center,
and right columns of the mask) and the vertical mask outputs 2 integers (the
input passed through the left and right columns of the mask. The center
column always outputs 0, and is thus optimized out).
- Edge_thresh: Second part of filter
mask(s). Input is 3 integers for the horizontal mask, and 2 integers
for the verticle mask. Output is a bit, asserted if there is an edge
for the pixel, and deasserted if there is not an edge. Each edge_thresh
represents a pixel. The input integers are the masked columns to the
left, center, and right of the pixel (left and right only for verticle mask).
The 2 verticle mask columns are summed together to find the verticle edginess
of the pixel and the 3 horizontal mask columns are summed together to find
the horizontal edginess. The absolute values of these two edginess values
is added together and compared to the threshhold. The output bit is
the result of this comparison.
- Output_director: Input is 4 edge bits,
a column integer, and a row integer. Output is a 32 bit word, a dataEnabled
bit, a column integer, and a row integer. The 4 edgebits are directed
into a word buffer. Each time the word buffer is complete (full of unoutputted
edgebits), it is output along with an dataEnabled bit for one clock cycle.
The output row and column are for the last nibble output.
- EdgeFilter: The main component which
which computes the edge bits. It determines if the input is image data,
assigns column and row numbers for that data, and blocks incoming data when
it is still processing the last of an image. It also stores and sends the
trailor data.
- 1 input_director which receives data from the Edgefilter's
input, or filler data when no input is avaliable (after the last pixel has
been read, but input_director still needs data to drive it).
- 4 pixelfilters which constantly take data from the input
director. The are numbered 2-5. Their output is sent directly to the
edge_threshes. Pixelfiters 4 and 5's output is also
stored in a register to use as output from virtual pixel_filter's 0 and 1
on the next word of directed input. If the input_director's columns
indicate that the pixels are along the left or right side of the image,
dummy values are sent
- 4 edge_threshes. Mapped to the input of edge_thresh
i are the left
columns of pixelfiter i-1, center columns
of pixelfilter i, and right columns from
pixelfilter i+1.
- 1 output_director to buffer the output from the edge_thresh
's and send a data enable signal when appropriate.