Optic Flow Module
- Interface
- Input: UDP Packet using signals from protocol wrappers, payload contains 1bpp of image data
- Output: UDP Packet using signals from protocol wrappers, payload contains vector data for each 8x8 pixel patch in the input image
- Design Subcomponents
- PatchMatch: Takes two NxN bit patches and outputs a '1' if they match.
- Encoder: Takes an N-bit one-hot input, and outputs a log2 N - bit number corresponding to the input that was a '1'.
- *Flow8x8: Takes a 22x22 bit field over which to search for a match to the 8x8 input. Uses 225 PatchMatch components and 1 256-bit Encoder. Output is a vector in the final output format (2 4-bit signed integers). Note: Vectors are in one's complement notation, any vectors containing an x or y component of 1000 should be ignored.
- ImageFIFO: Using the Asynchronous BlockRAM FIFO component created by CoreGen, has a width of 8 bits and a depth of 2047. A 320x200 image requires a depth of 2001 32-bit words in a FIFO.
- ShiftReg: An N-bit shift register which shitfs in S-bits of new data each clock cylce that the shift input is high. Resets to all zeros.
- Counter_n_bit: An N-bit counter, with reset and count enable signals.
- Payload: A component reused from my MP2 project which outputs a '1' when payload words are on the data lines. The Payload component does not use the DataEn signal, so that signal must be checked before utilizing the data from the upstream module.
- *OpticFlow:The main module which computes the optic flow.
- 4 Flow8x8 components to construct vectors (1-byte each) for 4 8x8 patches. This results in 32 new bits of image information used per clock cycle, and 32-bits of output data per clock cycle.
- 4 ImageFIFO components to emulate a 32-bit wide FIFO, which stores the previous image. Once an image is stored, the next frame triggers the reading of data from the FIFO, and the writing of new data to the back end of the FIFO. In this manner, one full image worth of data is always in the FIFO, which includes part of the current frame and part of the previous frame.
- 2 Width*(Patch+14)-bit ShiftReg components which shift in Width bits at a time. This stores 22 lines of the image data for optic flow analysis, and shift a new line in as it becomes available.
- 2 Width-bit ShiftReg components which shift in 32 bits at a time. These store the new line worth of data so that it can later be shifted into the larger ShiftReg components. For a 32-bit width, this simply acts like a register which is loaded every clock cycle, but is used for the sake of generality.
- 1 Counter_n_bit to count the data words to determine when the incoming image line is complete and ready for shifting into the image registers.
- 1 Payload component to determine when the image data can be read.
Note: The Encoder module has been replaced by an equivalent Encoder8 module which works for 256-bit input and 8-bit output. This design eliminates the for loop by using asynchronous logic of the form "00010001" when one_hot(17)='1' else...
* Some or all of the code for this component is hard-coded for a specific size. Flow8x8 assumes an 8x8 bit patch, and the OpticFlow module can accept any image width except for the following cases: The width must be evenly divisible by 32 (data word), the height must be evenly divisible by the patch height (which must be 8 as long as the Flow8x8 module is used), and the routing code for row00 through row21 must be changed if the width is larger than 32, since 32 is the only width for which the left edge and right edge of the image is evaluated at the same time.