Homework Assignment 3

Complete Homework

• Use the document editor of your choice to electronically generate solutions to your homework.
  Note that you will need to submit diagrams. Use an editor which makes creation of such easy.
• You may submit homework solutions as: a text (.txt), PostScript (.ps), Acrobat (.pdf), or Word (.doc) document.
  Acrobat (.pdf) is preferred.
• Submit Solutions to: Electronic Homework Server

Reading Material

• Lecture 9: System-Level Design with Automatically Generated Cores
• Lecture 10
• Embedded System Design: Chapters 5, 6, 10
• Read: Katherine Compton, Scott Hauck Totem: Custom Reconfigurable Array Generation
  IEEE Symposium on FPGAs for Custom Computing Machines Conference (FCCM), 2001
• Attend: Totem colloquium on Friday Oct 11 at 11:00am in Cupples II room 217.

Homework Questions

1. System On Chip (SoC) devices can combine aspects of custom design, standard cell design, and reconfigurable hardware.
   • Draw a schematic diagram that shows how a two-input NOR gate would be implemented in CMOS. The diagram should include: two inputs, an output, two NMOS transistors, and two PMOS transistors.
     (2 pt)
     
     
     
     
     
   • Draw a schematic diagram that shows how a four-input OR would be implemented in CMOS circuit. The diagram should include: four inputs, an output, several NMOS transistors, and several PMOS transistors.
     (2 pt)
     
     
     
     
     
   • Draw a schematic diagram that shows how a four-input OR gate would be implemented in a standard-cell ASIC that contains 2-input NOR gates as primitive elements. The diagram should include: four inputs, an output, and several 2-input NOR gates.
     (2 pt)
     
     
     
     
     
   • Complete the programming entry for an FPGA Look Up Table (LUT) to implement a 4-input OR gate.
     (2 pt)
     LUT[15..0] = __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __

2. Design tools enable reconfigurable hardware to be implemented efficiently.
   • Consider the function of the front-end FPGA synthesis tool (in our case, Synplicity). What information is contained in the resulting EDIF netlist?
     (2 pts)
     
     
     
   • Explain how simulated annealing is used to place components in traditional FPGAs.
     (2 pts)
     
     
     
   • Explain the fundamental reason why Programmable Interconnect Points (PIPs) add delay to propagation of signals on an FPGA.
     (2 pts)
     
     
     
   • Explain the term 'rip up and retry', as it relates to the routing of signals on an FPGA.
     (2 pts)
     
     
     

3. The Totem architecture generator combines aspects of reconfigurable hardware and custom design.
   • Describe the tradeoffs between specialized reconfigurable architectures and general purpose FPGAs.
     (2 pts)
     
     
     
   • Describe the differences between fine-grain components course-grained components
     (2 pts)
     
     
     
   • Explain why Totem arranges components such as RAM, ALU, and multipliers along a one-dimensional axis.
     (2 pts)
     
     
     
   • Explain what is meant by sharing wires in the Totem Architecture.
     (2 pts)
     
     
     
   • What types of applications achieve the greatest gains from Totem?
     (2 pts)
     
     
     
   • What types of applications would achieve the least benefit from Totem?
     (2 pts)
     
     
     
     

4. Desribe the variations between Fast Page Mode DRAM (FPM DRAM), Extended Data Out DRAM (EDO DRAM), and Synchronous DRAM (SDRAM).
   (3 pts)
   
   
   
   
   
   
   
   
5. High-level design of Integrated Circuits (ICs) can be simplified by using automatically generated cores. One type of core that will be an important component of Machine Problem 3 is a FIFO.
   • Run the Core Generator to implement a Synchronous FIFO.
     • The component should use block memory, not distributed memory
     • The FIFO should be 32 bits wide and 128 words deep
     • The device should have a data count output that is 8 bits wide
   • Write a VHDL testbench that uses the FIFO
     • Instantiate the FIFO component
       (2 pts)
     • Implement a state machine that writes 4 words to the device containing the values 11111111, 22222222 33333333, 44444444
       (2 pts)
     • Implement another state machine that waits until the four words are written into the FIFO, then reads them out.
       (2 pts)
     • Generate an output signal called CorrectOutput that goes high (active 1) if and only if the data is read correctly from the FIFO
       (2 pts)
   • Generate a .PDF version of the waveform that shows the data being written to the FIFO, the data being read, and the CorrectOutput signal going active.
     (2 pts)
   • Submit the VHDL for the testbench and the PDF of the waveform to the gradebot server

6. Draw schematic diagram that shows how a tool like CoreGen would implement a 32x2 (32 bits deep by 2 bits wide) memory using multiple 16x1 distributed memory elements The inputs to the circuit should be Address[4 downto 0], DataIn[1 downto 0], a write signal, and an enable signal. The output is DataOut[1 downto 0]. Assume that each of the primitive elements contains the signals Address[3 downto 0], DataIn, DataOut, an active-low write signal, and an enable signal.
   (4 pts)
   
   
   
   
   
7. Using the handshake protocol defined for the FPX SRAM interface, draw a timing diagram that shows how a device could acquire access to SRAM, write the the value 0x123412345 to M[5], and then release access. Relevant Signals are listed below:
   (6 pts: 1 pt/each for all signals except clk)
   
   • CLK
   • SRAM_REQ
   • SRAM_GR
   • SRAM_ADDR[17 downto 0]
   • SRAM_RW
   • SDRAM_D_IN[35 downto 0]
   • SDRAM_D_OUT[35 downto 0]