Homework Assignment 4

Complete Homework

• Use the document editor of your choice to electronically generate solutions to your homework.
  Note that you will need to submit diagrams. Use an editor which makes creation of such easy.
• You may submit homework solutions as: a text (.txt), PostScript (.ps), Acrobat (.pdf), Word (.doc), or PowerPoint (.ppt) document. Acrobat (.pdf) is preferred.
• Submit Solutions to: Electronic Homework Server

Reading Material

• Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matt Moe, and Reed Taylor, PipeRench: A Reconfigurable Architecture and Compiler in IEEE Computer, Vol.33, No. 4, April 2000

• H. Schmit, B. Levine and B. Ylvisaker, Queue Machines: Hardware Compilation in Hardware, in IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), April 2002

• Attend: Pipes, Queues, and other Abstractions for Reconfigurable Computing on Friday Oct 25 at 11:00am in Cupples II room 217.

Homework Questions

1. Explain how pipelines can improve the throughput of computation.
   (4 pts)
   
   
   
   
   
   
   
   
2. How many total clock cycles would be required to completely execute 4 pipelined instructions on a PipeRench-style machine that v=6 virtual pipeline stages and p=4 physical pipeline stages? Assume that the 1st and 2nd instruction need to use one set of custom pipeline logic while the 3rd and 4th instructions use anothter. Show a diagram of the configuration and execution phases for each Cycle and Stage like Figure 1b of PipeRench: A Reconfigurable Architecture and Compiler. (6 pts)
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   • Total number of clocks required to complete the 4 instructions = ___ clocks

3. Explain how a queue machine is different than a machine with a static Instruction Set Architecture (ISA)
   (4 pts)
   
   
   
   
   
   
   
   
4. Consider an original data flow graph that starts with inputs from functional units 1, 2, 3, and 4 and computes a final result using functional unit 8 [which is shaded]. Assume that the target queue machine has a stripe width of four queue machines.

   

   • Note: an editable, vector format of the diagram is available as: dataflow.ppt
   1. Draw the general DAG of the graph above.
      Note that all arrows should flow down
      (3 pts)
      
      
      
      
      
      
      
      
   2. Draw the leveled graph of the same.
      Insert Delay [D] units where appropriate
      (3 pts)
      
      
      
      
      
      
      
      
   3. Draw the compressed, leveled-planar graph of the same
      Insert Swap [S] units where appropriate, if needed
      (3 pts)
      
      
      
      
      
      
      
      
   4. Write the code generated by the traversal of the graph
      (3 pts)