Homework Assignment 5

Complete Homework

• Use the document editor of your choice to electronically generate solutions to your homework.
  Note that you will need to submit diagrams. Use an editor which makes creation of such easy.
• You may submit homework solutions as: a text (.txt), PostScript (.ps), Acrobat (.pdf), Word (.doc), or PowerPoint (.ppt) document. Acrobat (.pdf) is preferred.
• Submit Solutions to: Electronic Homework Server

Reading Material

• VHDL Reference that covers generics and generate statements
  
  • Generic is covered in Introductory VHDL, Section 8.4
  • The generate statement was discussed in Lecture 16.
• Synthesizable for loops
  • Covered in the Synplicity Reference Manual, around page 9-66.
• JDHL-related Material
  • Read: Brad Hutchings, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, Mike Rytting, A CAD Suite for High-Performance FPGA Design, FCCM 1999.
  • Visit: BYU JHDL Documentation Webpage
  • Attend talk: Reconfigurable Computing: Development Environments and Applications on Friday, Nov. 8, 11am in Cupples II, room 217
  • Meet with Dr. Hutchings on Friday, Nov. 8, 1:30 pm in Bryan 509c

Homework Questions

Consider the problem of coding the CAM matching function across a N-bit vector. Note that the logic function performed on each bit of the vector is identical and could be automatically generated using an automated process.
• Assume the inputs will be:
  • Pkt_Header: an N-bit vector containing values from the header packet
  • CAM_Value: an N-bit vector containing a value to match
  • CAM_Mask: an N-bit vector containing a mask with care/don't care bits
• Assume the output will be:
  • Match: A 1-bit result that is true if the CAM values match the packet's address for all of the the unmasked bits.
1. Draw the schematic for the circuit that implements one bit of the CAM match function as a function of one bit from each of the Pkt_Header, CAM_Value, and CAM_Mask inputs.
   (3 pts)
   
   
   
2. Describe, in words, how each bit of a N-bit vector could be combined to implement the single Match output.
   (3 pts)
   
   
   
   
   
3. On a separate page, Write a program in C, Java, or Perl that generates VHDL to implement an N-bit CAM function.
   (5 pts)
   • Run the program and show the resulting VHDL code
     (2 pts)

4. On a separate page, Write VHDL code that uses the 'generic' and 'generate' statements to implement the N-bit CAM function.
   (5 pts)

5. On a separate page, Write JHDL that implements an N-bit CAM matching function
   (5 pts)
   • The first line of your program should be:
     public NBitCAM(Wire Pkt_Header, Wire CAM_Value, Wire CAM_Mask)
     
     

   • Is JHDL appropriate for structural or behavioral designs? Explain.
     (3 pts)
     
     
     
     
     
   • Explain the purpose of the JHDL Tech Mapper class.
     (3 pts)