CS/COE 536M Fall 2002

Reconfigurable System-On-Chip Design

J. W. Lockwood

• Lecture 1: Motivation for Reconfigurable System On Chip (SOC)
  • System On Chip Design
  • Processors, PLD, ASICs, and VLSI
  • Moore's Law
  • Economics of NRE and Time-to-Market
  • The Field-programmable Port Extender (FPX)
• Lecture 2: VHDL and State Machines for processing Protocols
  • Language-based Design
  • Entity Declaration
  • Behavioral and Structural Architectures
  • VHDL Constructs: Combinational and sequential circuits
• Lecture 3: Internet Packet processing on the FPX
  • Packet processing operations in firewalls and routers
  • Network packet formats
  • Layered Protocol Wrappers
  • Packet classification with TCAMs
• Lecture 4: Implementation of the CAM-based firewall in reconfigurable hardware
  • Firewall state transitions
  • CAM Updates
  • FPX hardware design flow
• Lecture 5: Evaluation and Testing of Firewalls in Reconfigurable Hardware
  • Testbench configuration for simulation
  • FPX Hardware configuration for in-system testing
• Lecture 6: Content-based Packet Processing in reconfigurable hardware
  • Content matching vectors
  • CAM Filters with content match field
  • Range matching with TCAMs
• Lecture 7: Implementation of the SPAM filter
  • The content matching module$
  • Generating testbenches with ASCII strings
• Lecture 8: Class-based and Flow-based Queuing Systems
  • Class-based and Flow-Based Queuing
  • The fluid fair queue model
  • Packetized Generalized Processor Sharing (PGPS)
  • Round Robin Queuing
  • The 3DQ Architecture
• Lecture 9: System-Level Design with Automatically Generated Cores
  • Soft, hard, and hybrid cores
  • Core Generators
• Lecture 10: Custom, ASIC, and FPGA Circuit Implementations
  • CMOS Integrated Circuit components
  • Standard cell layout
  • Configurable Logic Blocks (CLBs)
  • Placement and Routing
  • Properties of Programmable Interconnect
• Lecture 11: Implementation of Hybrid Priority and Per-Flow Queuing Systems in Reconfigurable Hardware
  • Machine problem 3 layout
  • Generation of flow identifiers
  • Flow data structure
  • Service List
  • Enqueue and Dequeue operations
  • System initialization
  • Data structure management in SRAM
• Lecture 12: Random Access Memory
  • On-chip SelectRAM and BlockRAM
  • Zero-Bus Turnaround SRAM (ZBT-SRAM)
  • Dynamic RAM (FPM, EDO, SDRAM)
  • Using arbitrated memory interfaces on the FPX
• Lecture 13: Hybrid Reconfigurable Systems
  • Chameleon Multi-context reconfigurable logic
  • CMU Piperench
  • CMU Queue Machines
  • Tensilica Configurable SOC Processor Core
• Lecture 14: Final Projects
  • Goals of the final project
  • Helpful hints
  • Grading
  • Project Presentation Template
• Lecture 15: Midterm Notes and Issues for Final Project Integration
  • Material to be covered on the Midterm Exam
  • Duplex firewall configuration
• Lecture 16: Alternative Tools for Hardware Design
  • Using high-level tools to generate low-level hardware
  • VHDL Generate statement
  • The BYU JHDL Tools
• Lecture 17:
  • Project Testing
  • Project Integration
  • Project Submission
• Lecture 18:
  • Submitting Projects to the Project Integration Server
  • Read Integration Server Worksheet