E71 CS 6812 - Research Seminar on Reconfigurable Hardware
Fall 2002
- Description:
In this seminar, we will review current conference and journal papers
related to the design of reconfigurable hardware systems. In particular,
we will choose papers that focus on topics related to reconfiguration
techniques for systems with Field Programmable Gate Arrays (FPGAs),
techniques of migrating algorithms from software to hardware,
and study applications for FPGAs in computer networks.
- Instructor:Prof. John W. Lockwood
- Credits:
- Class Format
- Seminar
- Review 1 paper per week
- Rotating schedule of presentations
- Group discussion
- Time:
- Wednesdays at 11:00am to Noon
- Place:
- Jolley 509c (conference room in main CS office)
- Readings
- Campbell A.T., De Meer H.G., Kounavis M.E., Miki K.,
Vicente J., and Villela D.,
A Survey of Programmable Networks,
Computer Communications Review, April 1999
- R. Franklin, D. Carver, B. L. Hutchings,
Assisting Network Intrusion
Detection with Reconfigurable Hardware, FCCM'02.
- Michael J. Wirthlin, Brian McMurtrey,
IP Delivery for FPGAs Using Applets
and JHDL, DAC'02.
[Slides].
- Adam Donlin,
Self Modifying Circuitry -
A Platform for Tractable Virtual Circuitry, FPL'98.
- Steve Casselman, John Schewel,
Net Aware BitStreams that Upgrade FPGA
Hardware Remotely Over the Internet,
Proceedings of SPIE, volume 4867, Boston, MA, July 30 2002
- Zhining Huang and Sharad Malik,
Exploiting Operation
Level Parallelism through
Dynamically Reconfigurable Datapaths,
DAC'02,
[Slides]
- Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott
Experimental Testing
of the Gigabit IPSec-Compliant
Implementations of Rijndael and Triple DES Using
SLAAC-1V FPGA Accelerator Board, 2001
- Bill Salefski, Re-Configurable Computing in Wireless, Design Automation Conference, 2001.
- Marcel Waldvogel,
Mithos:
Efficient Topology-Aware Overlay Network (Special Seminar)
- Michael Wirthlin,
Sequencing Run-Time Reconfigured
Hardware with Software, ACM/SIGDA International Symposium
on Field Programmable Gate Arrays, pp. 122-128 (1996).
- Optional: Burton H. Bloom
Space/Time
Trade-offs in Hash Coding with allowable Errors,
Communications of the ACM, volume 13, Number 7, July 1970.
- Assigned: Andrei Broder and Michael Mitzenmacher,
Network Applications
of Bloom Filters
- Ch. YkmanCouvreur, J. Lambrecht, D. Verkest, F. Catthoor,
A. Nikologiannis, G. Konstantoulakis
System-level performance optimization
of the data queueing memory management in high-speed network
processors
DAC'02,
- Seminar Survey:
Praveen 11/20/02
- N. Shirazi, W. Luk, P.Y.K. Cheung, Framework and Tools for Run-Time Reconfigurable Designs, IEE Proceedings Computers and Digital Techniques, Vol. 147, No. 3, May 2000, p. 147 - 152.
- Seminar Survey:
Hui 12/04/02
- On-line References
- Related Links
- More reading available from: