Today's Topics

• PC Hardware Interface via Ports
  1. IN/OUT Instructions
  2. Keyboard
  3. 8253 Timer
  4. Parallel Port
  5. Joystick

In/Out Instructions

• I/O ports on the PC
  • Uses same Address/Data lines as memory
  • Like memory, but limited to 16-bit (word-size) addresses
  • Has separate IOR/IOW (read & write) signals on bus
  • Access ports with IN and OUT opcodes
  • Devices which use I/O bus
    • Keyboard
    • Speaker Control
    • Parallel Port
    • Serial Ports
    • Sound Cards
    • Network Cards

• IN/OUT Opcode Limitations
  • Uses accumulator register for data (AL or AX)
  • Immediate port address possible for 8-bit potrt address (0000h-00FFh)
  • Register port address permits full 16-bit address (0000h-FFFFh)
  • No segment:offset addressing

• IN accumulator, port:
  • Read to AL value at [port 61]
    

    IN AL,61h

  • Read to AL value at [port 1234h]

    MOV DX, 1234h IN AL,DX

• OUT port-number, accumulator:
  • Write to [port 61] value of AL
    

    OUT 61h,AL

    
    
  • Write to [port 1234h] value of AL

    MOV DX, 1234h OUT DX,AL

    
    

Keyboard

• User presses or releases button

• Buttons read by on-board Intel 8048 Microcontroller
  • Microcontroller De-bounces buttons
  • Generates scan code(s)
  • Prefixes extended keys with 224 (EOh)

• Microcontroller serially transmits Scan codes at 10,000 baud to parallel latch on motherboard
  • IRQ1 Triggered when complete byte arrives.
  • Data available at Port 60h
  • Acknowledge Keyboard: (toggle bit 7 of port 61h)
    (See Lab manual for details)

• INT9 Called to process keystroke (usually BIOS)
  • Default BIOS routine tracks [shirft], [alt], [ctrl], [CapLock], [NumLock] status word
  • Keyboard buffer holds keystrokes until read by INT16 (KBDIN)

• See Feldman's GPE Keyboard Ovewrview
• See ECE291 Lab Manual

8253 Timer

• Intel 8253 contains 3 independent timers
  • Channel 0: System Timer Interrupt 18.2/sec
  • Channel 1: Memory Refresh
  • Channel 2: Speaker

• 8253 Clocked by common 1,193,180 Hz clock

• 8253 Uses Multiple Port Addresses

  Port	Description
  40h	Channel 0 Count Register
  41h	Channel 1 Count Register
  42h	Channel 2 Count Register
  43h	Timer Control (See Below)

• Timer Control Port

  Bits	Description
  7,6	Channel ID (00,01,10)
  5,4	00: latch count for reading 01: Read/Load high byte 10: Read/Load low byte 11: Read/Load low byte then high byte
  3,2,1	Count Mode (011=Square Wave)
  0	Count Method: 0=Binary, 1=BCD

• Speaker Control
  • Diagram on board
    • Timer Output from 8253
    • Gate control (port 61h, bit 1)
    • Speaker Enable AND gate (port 61h, bit 0)
    • Driver/Low-Pass Filter
    • Speaker

  • Write to Control Port
    

    MOV AL,10110110b OUT 43h,AL

    • 10: Control timer 2
    • 11: Load Low Byte then High Byte
    • 011: Select Square wave output
    • 0: Count in binary

  • Enable Speaker

    IN AL,61h OR AL,00000011b OUT 61h,AL

    • Bit 1: Enable Timer
    • Bit 0: Enable Speaker
    • Don't change other bits

  • Write Count to timer

    OUT 42h, AL MOV AL,AH OUT 42h, AL

    • AX=count (ticks) = 1193180 (ticks/sec) / Freq (1/sec)

  • Tones produced by square wave

  • Try BEEP.ASM for a funtional demo

  • See Timer/Speaker FAQ for more information.
  • See ECE291 Lab Manual

Parallel Interface

• Originally Designed for printers

• Provides 8-bit I/O

• Attaches via 25-pin or Centrontics connector

• Provides TTL-level (5V) external I/O

• Major Signals

  Signal(s)	Input/ Output	Notes
  Data[7:0]	Bidirectional	Byte-wide data bus
  Strobe	To device	Write signal
  Busy	From device	Don't send more data
  Ack	From device	Acknowledge (interrupt signal)
  Initialize	To device	Initialize external device
  Out of Paper	From device	Status signal

  
  

• Writing to the parallel port

  

• Using an ISR to handle interrupt
  • Avoids waiting for BUSY to fall
  • Rising edge of ACK triggers IRQ 5/7
  • Configure LINUX for polling or interrupt
    /usr/src/linux/drivers/char/lp.c and
    /usr/include/linux/lp.h

• Provides easy interface to the PC
  Just redefine meaning of the signals and attach your hardware to the computer

• PC may have up to three LPT devices.
  Each device has a unique Port I/O address

  Device	Data Port	Status Port	Control Port
  LPT0:	3BCh	3BDh	3BEh
  LPT1:	378h	379h	37Ah
  LPT2:	278h	279h	27Ah

• Control Port

  Bit	Description
  7-5	Unused
  4	IRQ Enable
  3	Select [inverted]
  2	/Initialize
  1	AutoFeed [inverted]
  0	Strobe [inverted]

  
  /Signal: Active Low [example: /Strobe : 0=strobe]
  [inverted]: Value complemented by hardware

• Status Port

  Bit	Description
  7	/Busy [inverted]
  6	Ack
  5	Out-of-Paper
  4	Selected
  3	I/O Error
  2-0	Unused

• See Parallel Port FAQ for more information.
• See ECE291 Lab Manual
  • Use resistors to avoid damage to TTL buffers
  • Making use of other I/O signals

Joystick Inteface

• Low-cost "A/D converter"

• Uses T=RC time constant to determine postion
  • Schematic Diagram on board
  • 100K Ohm Variable resistor
  • Capacitor
  • Comparator (Changes at transistion point)

• Connects via DB15-S connector
  • Each port supports two joysticks (A & B)
  • Each joystick has X,Y analog coordinates
  • Each joystick has 2 (unbounced) digital buttons
  • Total of 4 Analog and 4 digital inputs

• Conrol / Status Register: Port 201h

  Bit	Pin Number	Description
  7	14	Joystick B: Button 2
  6	10	Joystick B: Button 1
  5	7	Joystick A: Button 2
  4	2	Joystick A: Button 1
  3	13	Joystick B: Y-Coordinate
  2	11	Joystick B: X-Coordinate
  1	6	Joystick A: Y-Coordinate
  0	3	Joystick A: X-Coordinate

• Theory of Operation
  • Issue OUT 0x201 to begin capacitor discharge

  • Issue IN 0x201 to read status

  • Repeat reading status until analog signals go low
    • Use polling to count cycles
    • No IRQ available for joystick

  • Calculate T = 24.2 usec + 0.011 * R
    to determine position

  • Calibration often required, as CPU speed affects count

• Show hardware

• See Joystick FAQ for more information.
  • Avoid damage to hardware by NOT shorting Vcc/GND