CSE306 - Lecture 24

CSE306

Processing Systems and Structures

J. W. Lockwood

Lecture 24

Today's Topics

MMX : MultiMedia eXtensions
SIMD FPU (3D-NOW)
SIMD FPU (SSE)

MMX: MultiMedia eXtensions

Single-Instruction-Multiple-Data (SIMD)
New instructions first available in Spring 1997
- Supported on
  - Intel Pentium-MMX, Pentium II, Pentium III, Pentium IV (and later)
  - AMD K6, K6-2, K6-3, Duron, Athlon (and later)
  - Cyrix M2, MMX-enhanced MediaGX, Jalapeno (and later)
  - Winchip, Winchip2 (and later)
- NOT supported on
  - 8088-80486
  - Intel Pentium (original) / Pentium Pro (and earlier)
  - AMD K5 (and earlier)
  - Cyrix 6x86 (and earlier)
Uses 64-bit mantissa portion of 80-bit FPU registers
- Avoids modification to Multitasking operating system
- Preserves FSAVE/FRSTOR functions for cooperative multitasking OS
- Sets Task Switch (TS) bit for preemptive multitasking OS
  - TS=1 on context switch
  - FPU generates INT7 (Device not available) for MMX/FP opcode when TS=1
  - Operating system restores FPU state and set TS=0
64-bit entities Packed (P) entities
- Eight 8-bit packed bytes (B)
- Four 16-bit packed words (W)
- Two 32-bit packed doublewords (D)
- One 64-bit quadword (Q)
Operations
- Transfer
  - MOVQ Dest, Source : 64-bit move
    One or both arguments must be a MMX register
  - MOVD Dest, Source : 32-bit move
    Zeros loaded to upper MMX bits for 32-bit move
- Arithmetic
  - PADD(B/W/D): Addition (Byte/Word/Double)
  - PSUB(B/W/D): Subraction
  - PMUL(L/H)W: Multiplication (Low/High Result)
- Logical
  - PAND: Logical AND (64-bit)
  - POR: Logical OR (64-bit)
  - PXOR: Logical Exclusive OR (64-bit)
  - PANDN: Destination = (NOT Destination) AND Source
- Shifting
  - PSLL(W/D/Q): Packed Shift Left (Logical)
  - PSRL(W/D/Q): Packed Shift Rigth (Logical)
  - PSRA(W/D/Q): Packed Shift Right (Arithmetic)
- Comparisions
  - PCMPEQ: Compare for Equality Sets Result Register to ALL 0's or ALL 1's
  - PCMPGT: Compare for Greater Than
    Sets Result Register to ALL 0's or ALL 1's
- Unpacking (Increasing data size by 2*n bits)
  - PUNPCKLBW: Reg1, Reg2: Unpacks lower four bytes to create four words.
  - PUNPCKLWD: Reg1, Reg2: Unpacks lower two words to create two doubles
  - PUNPCKLDQ: Reg1, Reg2: Unpacks lower double to create Quadword
- Packing (Reducing data size by 2*n bits)
  - PACKDW Reg1, Reg2: Pack Double to Word
    Four doubles in Reg2:Reg1 compressed to Four words in Reg1
    Diagram on board
  - PACKWB Reg1, Reg2: Pack Word to Byte
    Eight words in Reg2:Reg1 compressed to Eight bytes in Reg1
    Diagram on board
Saturation/Wraparound Arithmetic
- Wraparound: carry bit lost (significant portion lost)
- Saturation: Overflow/Underflow clipped to low/high values (add S)
- Unsigned Saturation: (add US)
Example
- Adding 8 8-bit integers with saturation
  
  Yields: mm0=80807F5480807F54h
  80h+0=80h (addition with zero)
  80h+90h=80h (saturation to maximum negative value)
  55h+33h=7fh (saturation to maximum positive value)
  55h+FFh=54h (subtraction by one)
Storage of MMX data in FPU Registers
- Benefit: Existing operating systems preserve FPU registers on context switch.
- Disadvantage: Mixing FPU and MMX opertions can be slow.
  - Any MMX opcode sets ALL FPU tag bits=0 (valid)
  - EMMS opcode to mark ALL FPU tag bits=1 (empty)
  - FPU operations sets/clears tag bits as register used
Programming Hints
- NASM supports MMX Instructions
- MASM 6.13 patch for MASM 6.11: Supports MMX and 3D-NOW instructions
Documentation
- K6 Multimedia Extensions (MMX) (.pdf)

SIMD FPU (3D-NOW)

Parallelism like MMX for FPU Operations
- Operates on IEEE-754 Single-precision 32-bit Reals
- Utilizes 64-bit wide data path (2 32-bit reals/instruction)
- Superscaler processor executes two parallel 3D-Now operations per clock,
  Provides 4 32-bit FPU operations/clock.
- Competes with SSE
21 New instructions first available in May 1998
- Supported on
  - AMD K6-2-3D
  - AMD K6-3
  - AMD K7 (and later)
  - WinChip2 (and later)
  - Cyrix/National Semiconductor Jalapeno core (and later)
- NOT Suported on
  - Intel processors
  - AMD K6 (original), K5 (and earlier)
  - Cyrix/National Semiconductor M2, 6x86 (and earlier)
Representative Instructions
- PFADD (addition)
- PFSUB (subtraction)
- PFMUL (multiplication)
- PFRCP (Reciprocal)
- PFRSQRT (Reciprocal Square root)
- PF2ID Converts Packed Floats to Integer Doubles [32-bit])
- PFCMP[EQ/GE/GT]
FPU Operation
- Rounds FP results to nearest
- Saturates +/- Max values
Storage of 3D-NOW data in FPU Registers
- No different than storage of MMX data in FPU registers.

Programming Examples

; K3D = 3D-Now optimized Code ; .. data section .. x_12 dd 1.0 ; Pair of 32-bit reals dd 2.0 x_34 dd 3.0 ; Pair of 32-bit reals dd 4.0 m dd 3.141592654 ; Duplicate values to fill dd 3.141592654 ; both 32-bit parts of b dd 10.25 ; of 64-bit number dd 10.25 y_12 dd ? dd ? y_34 dd ? dd ? ; .. code section .. MOVQ mm1,x_12 MOVQ mm2,x_34 MOVQ mm3,m MOVQ mm4,b PFMUL mm1,mm3 ; Compute: y[i] = m * x[i] + b PFMUL mm2,mm3 ; for i = (1,2,3,4) PFADD mm1,mm4 ; In Parallel using Superscaler PFADD mm2,mm4 ; 3DNow instructions. MOVQ y_12,mm1 MOVQ y_34,mm2

Programming Hints
- Install MASM 6.13 patch to MASM 6.11 for support of MMX and 3D-NOW instructions
- Avoid NaN's
Performance Optimization
- Minimize data dependency between adjacent instructions.
Documentation
- AMD 3D Technology Manual (.pdf file)
- AMD Software Developer site.

Streaming SIMD Extensions (SSE)

Parallelism like MMX for FPU Operations
- Operates on IEEE-754 Single-precision 32-bit Reals
- Utilizes 128-bit wide data path
- Provides 4 32-bit FPU operations/clock
- Formerly known as Katmai
- Competes with 3DNow
70 New instructions first available in March 1999
- Supported on
  - Intel Pentium III
- NOT Suported on
  - Intel Pentium (original)
  - Pentium-MMX
  - Pentium Pro
  - Pentium II
  - Pentium II - Xeon (or earlier)
  - All Non-Intel processors
Representative Instructions
- addTT (addition)
- subTT (substraction)
- mulTT (multiplication)
- rcpTT (Reciprocal)
- rsqrtTT (Reciprocal Square root)
- cvttps2pi Converts Packed Floats to Integer Doubles
FPU Operation
- Rounds FP results to nearest
- Saturates +/- Max values
Storage of SSE data
- Requires new registers
- OS must preserve these registers for context switch
Programming Hints
- Avoid NaN's
Documentation
- Intel - Software Developer's Manual; Volume 2. Appendix C