INSTRUCTOR

• Prof. John W. Lockwood :
  • Email: lockwood@arl.wustl.edu
    
  • Office Hours: By Appointment
  • Location: 522f [Enter through Bryan 522]

GRADER

• Azuka Dike
  • Email: acd1@cec.wustl.edu
  • Location: Urbauer 114
  • Office Hours: Tuesdays 6pm-8pm

HOMEWORKS

• Assigned on Thursday
• Due 1 week later at start of class.

PREREQUISITE

• EE 260M or equivalent

LECTURES

• Time: Tue and Thr : 2:37 - 4:00 pm
• Location:
  • Classroom: Urbauer 116

TEXTBOOKS/READING

• Required
  • Gary D. Hachtel and Fabio Somenzi, 'Logic Synthesis and Verificatoin Algorithms', Kluwer Academic Publishing, 1998.
• Supplemental
  • John W. Lockwood: 'Logic Synthesis for Field Programmable Gate Array (FPGA) Technology, Chapter 65 in VLSI Handbook, Wai-Kai Chen, editor. IEEE Press, 1999.

WEBSITE

• http://www.arl.wustl.edu/~lockwood/class/cse460/

TOOLS

• Cygwin Tools: Freeware GNU Software (g++/gcc)

CREDITS

• 3 units
  • Design: 1.2 units
  • Engineering science: 1.8 units

GRADING

• Homework & Programming Assignments (60%)
• Final Exam (40%)

COURSE OUTLINE

• Introduction to Design Automation

• Switching Theory
  • Sets and Relations
  • Partial Orders
  • Hasse Diagrams
  • Lattice
  • Atoms
  • Boolean Algebras

• Logic Synthesis
  • Two-level Logic synthesis
  • Quine/McCluskey Method
  • Unate Covering
  • Incomplete Specification
  • Computational Techniques

• Multi-level Logic Synthesis
  • Technology Mapping to CMOS/NMOS/PMOS
  • Decomposition
  • Technology Mapping to LUTs with Chortle
  • Binary Decision Diagrams

• Sequential techniques
  • Finite state machines.
  • Synchronous circuits
  • State tables
  • State assignment
  • Synthesis and verification
  • Finite Automata