Course Announcement for Fall 2003
E61 CS 535M / CoE 535 / EE 535:
Acceleration of Algorithms in Reconfigurable Hardware
As the Internet continues to be used for more applications,
computer networks will perform more functions.
In order to implement these new functions at full speed,
much of the data processing operations will be implemented
in hardware. This class will explore the techniques of
migrating networking algorithms from software to hardware.
Machine problems will be implemented that cover
processing and queueing data in Field Programmable Gate Arrays (FPGAs).
- Prerequisites:
- Experience with hardware design and VHDL synthesis
- EE260/CS260M, CoE/EE/CS362, CoE/EE/462 or equivalent
- Experience with computer networks
- CS423S, CS533M, or equivalent
- Textbooks/Readings:
- Select Readings from networking conferences and journals
- Sudhakar Yalamanchili, VHDL: Starter's Guide: From Simulation to
Synthesis, 1999, ISBN 0-13-080982-9 (In Bookstore)
- Instructor:Prof. John W. Lockwood
- Credits: 3 units
- Engineering Science: 1.5 Units
- Engineering Design: 1.5 Units
- Class Format
- Lecture (once per week)
- Theory of hardware-based computation
- Practice of FPGA-based design
- Project Laboratory (once per week)
- Individual programming assignment (first half of class)
- Final Project (second half of class)
- Course Topics
- Reconfigurable Hardware Design Flow
- Modular Hardware Design Techniques
- Synthesis of hardware modules in Field Programmable Gate Arrays
- Performance Analysis and Optimization
- Assignments
- Homeworks
- Machine Problems
- Final Project
- Class Webpage
- Related Past Courses