For the following questions, review the Lecture notes
from Lecture 7 and
Lecture 8.
- Suppose that you wanted to use the 104-bit TCAM discussed in class
to search for headers of IP packets. Describe how you would program
the TCAM to find packets with the following properties: (4 pts)
- Source Address = 128.252 / 16
- Destination Address = 192.168.50 / 8
- Source Port = Whatever
- Destination Port = 80 [decimal]
- Protocol = TCP
Value =
___ ___ ___ ___ : ___ ___ ___ ___ : ___ ___ : ___ ___ : ___
(Hex Bytes)
Mask=
___ ___ ___ ___ : ___ ___ ___ ___ : ___ ___ : ___ ___ : ___
(Hex Bytes)
- Suppose that you had a 16-byte TCAM that could be used to search
for strings in the network content. Describe how you would program
the TCAM in order to locate a string that contained the following
content: (without the Quotes) (4 pts)
Value = ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ (ASCII letters)
Mask = ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ (Hex)
How many copies of the same TCAM hardware do you need in order to
perform byte-size searches when data enters the system as
32-bit word-size values? (1 pt)
______ copies
If each each bit of a TCAM could be computed using one LUT,
how many total LUTs are needed to implement the byte-size
scanner in the word-sized system? (1 pt)
______ LUTs
- In the data given for the TCP dump example of the
Evening Star poem, how many packets were required to
fetch the poem from the web server? (3 pts)
- B2S.packets = __________ packets from Browser to web server
- S2B.packets = __________ packets from Web server to Browser
- Total.packets = __________ packets
For the entire transaction (all packets), how many total bytes were transferred over the network? (3 pts)?
- B2S.bytes = __________ bytes from from Browser to web server
- S2B.bytes = __________ bytes from Web server to Browser
- Total.bytes = __________ bytes
Of the data transferred, how many bytes were actual data in the poem?
(1 pt)
- Poem.bytes = __________ bytes
Of the data transferred, how many bytes were needed to specify the
/path/filename that the browser wanted to GET?
(1 pt)
- Path.bytes = __________ bytes
What fraction of data sent over the network actually contained
useful information? (2 pts)
- ( Poem.bytes + Path.Bytes ) / (Total.bytes) = ________ %
For the following questions on the Scan Circuit,
use should download the MP2 distribution from CVS.
As with MP1, You can access the files using a command like:
- export CVS_RSH=/bin/ssh
- export CVSROOT=username@soc.arl.wustl.edu:/usr/local/cvsroot
- cvs co -P username/MP2/
Name the process that assigns values to the oth_out signals
(hint: use grep) (3 pts).
________________
Name the process that you will have to update to change when
stats packets are sent. (3 pts)
________________
Cores allow circuits to be implmented quickly by
instantiating hardware that has already been designed.
The CoreGen tool automatically generates cores that can
be parameterized to meet the needs of a particular circuit.
To use CoreGen,
follow the steps below to generate a FIFO:
a. Log onto SOC with X forwarding enabled (using the -X or -Y
flags to SSH)
b. Check out the [username]/MP2 distribution from
CVS
c. Go to the MP2 directory and run "source synset"
d.
Run "coregen &"
e. When the "Getting Started"
window comes up, click "Create a New Project" (if this
does not appear, go to File->New Project...)
f. Under
"Directory" pick a directory of your choice. You may want
to create a "coregen" directory in your home directory and
use that
g. Under "Output Options" select "Flow
Vendor"
h. Under "Target Architecture" select
VirtexE
i. Under "Design Entry" select "VHDL"
and "Synplicity" and select "OK"
j. On the
left, double-click "Memories & Storage Elements"
k.
From the expanded tree, double-click "FIFOs"
l. On the
right, double-click "Synchronous FIFO"
m. Name the
component whatever you want (i.e. "my_fifo")
n. Under
Memory Type select "Block Memory"
o. Under "Data
Width" select however many bits you want (say, 40) per value
p.
Under "FIFO Depth" select how many of these 40-bit values
you want the FIFO to be able to hold
q. Press "Generate"
r.
When it says that the FIFO has been successfully generated, click
"OK" and exit Coregen
s. Go to the directory that you
saved the coregen project to (in my case, it's
/home/jeff/coregen)
t. Copy the "my_fifo.vhd" file to
your MP2/vhdl directory
u. Copy the "my_fifo.edn" file
to your MP2/syn/rad-xcve2000-64MB directory
v. Now, you can add
the FIFO as a component in your Scan project just like any other
component (see, for instance, the control_proc.vhd file for
examples)
Answer the following questions:
List the name and decribe the purpose of
each signal created by the Coregen FIFO: (5 pts)
- _________ : _________________________________________
- _________ : _________________________________________
..
- _________ : _________________________________________
FIFOs serve as a useful mechanism to pass data between
modules in a circuit. Producers can operate asynchronously
from the consumers of the data. We will use FIFOs in the MP2
assignment to communicate between the Control Processor and
the Scan Module. Based on the code in the MP2 project,
What VHDL files will you have to change to use a FIFO
to communicate between the Control Processor and the Scan module?
(4 pts)
____________________________________________________________
____________________________________________________________
..
____________________________________________________________
Write VHDL code to implement a 24-bit counter named COUNTER
that has synchronous high-valued reset (when RESET = '1' the counter
should return to zero). The counter only counts when CNT_EN = '1',
otherwise it retains its previous value. When the counter reaches
15,328,179 the counter should set signal TRIGGER high for one clock
cycle and resume counting from zero. (5 pts)
You may work with the following assumptions:
Signals RESET, CNT_EN, and TRIGGER are already defined as
std_logic
Signal COUNTER is already defined as std_logic_vector(23
downto 0)
You have a clock signal named CLK and all events should
happen on the rising edge.
|
<![CDATA[
CNT_EN : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNTER : OUT STD_LOGIC_VECTOR(23 downto 0);
TRIGGER : OUT STD_LOGIC;
TwentyFour_Bit_Counter : process (CLK)
begin
end process TwentyFour_Bit_Counter;
]]> |
Coregen can be used to implement counters. Implement the
same counter as in #5 using Coregen (use a count enable signal and
restrict the count to the same value as above, but you do not need
to have a trigger signal). List the settings you used in your
component (i.e. list any settings that you changed in the
Grahical User Interface (GUI) different from the defaults). ( 5 pts)
___________________________________________
___________________________________________
..
___________________________________________
- Based on the amount of time and effort to create the
Counter using both methods, which would you prefer to
use to design a circuit ? Explain.
________________________________________________________
________________________________________________________
________________________________________________________