CSE 566M Fall 2004

Reconfigurable System-On-Chip Design

John W. Lockwood

• Lecture 1: Introduction to Reconfigurable System On Chip
  • About the CSE566 Course: Website, instructor, course format
    textbooks and reading material, message board, grading, projects.
  • Moore's Law
  • Economics of NRE and Time-to-Market
  • Examples of Systems on Chip

• Lecture 2: Logic and Integrated Circuit Technologies
  • Basic Logical Functions and their implementation in circuits
  • CMOS Integrated Circuit components
  • Full Custom layout
  • Standard cell layout
  • RAMs and LUTs
  • FPGAs

• Lecture 3: Language-based Hardware Designs
  • Comparison of Schematic and Language-based Design
  • VHDL Architecture and Behavioral Descriptions
  • Process statements
  • CASE and IF/THEN/ELSE constructs

• Lecture 4: Synchronous Storage & Finite State Machines
  • Edge-triggered Flip/Flops
  • State Declarations and encodings
  • State machine implementations and state transition assignments

• Lecture 5: Management of Large SoC Project Designs
  • Version control systems
  • Concurrent Versions System (CVS).
  • Structure of a CVS project
  • Common CVS commands
  • Remote access with Secure Shell (SSH)
  • Making use of tools in Cygwin

• Lecture 6: Transmission Control Protocol / Internet Protocol (TCP/IP) Processing with Layered Wrappers
  • Transport of data through the Internet with TCP/IP
  • TCP/IP session handshake and segmentation into packets
  • The FPX platform
  • Network configurations
  • TCP/IP data waveforms
  • The PortTracker application
  • Signal Waveforms for Machine Problem 1

• Lecture 7: Scanning Data with the Transmission Control Protocol / Internet Protocol (TCP/IP) Wrappers
  • Interaction on TCP processor and Scan circuit
  • Scan application communication to TCP, control processor, and memory
  • Ternary Content Addressable Memory (TCAM)
  • Packet header matching with TCAMs
  • Sample filter specification
  • String matching with TCAMs

• Lecture 8: Content Analysis with the Scan Module
  • Network configuration of Servers, hosts, and TCP processing hardware
  • Web content example
  • TCP Dump of web transaction
  • TCP Protocol wrapper signals of same transaction

• Lecture 9: COREs
  • Logic Cores
  • Core Generators
  • Alliance Cores,
  • OpenCores.org

• Lecture 10: Memories
  • Distributed Random Access Memory (RAM)
  • BlockRAM on the VirtexE FPGA
  • Zero-Bus Turnaround (ZBT) Static SRAM
  • Synchronous Dynamic RAM (SDRAM)

• Lecture 11: Pipelines and Retiming
  • Pipelines to increase performance
  • Latency
  • Maximum clock frequency
  • Retiming

• Lecture 12: Using the TCP Processor
  • Motivations for TCP-Processor
  • Laboratory setup for live traffic processing
  • Project ideas for CSE566
  • Tools & Debugging Techniques

• Lecture 13: Robust TCP reassembly in the Presence of Adversaries
  • Motivations for robust TCP flow reassembly
  • Measurements of trace data
  • Buffer occupancy
  • Data structures and pseudocode for buffering packets

• Lecture 14: Final Project Template
  
  • Title, Team,
  • Objective, Goals, Utility
  • Related work, Approach
  • Metrics, Project value
  • Project planning, website
  • (Slide template in PowerPoint format)

• Lecture 15: Laboratory Configuration for Hardware Testing
  • FPX Hardware configurations
  • Use of eGroupWare's Filemanager to upload bitfiles
  • Reset and reprogramming of the hardware
  • Using SRAM dump to see results of processed traffic
  • Viewing results in the file manager
  • Logout

• Lecture 16: Peer Evaluations
  • Technical Merit and Accomplishment Scores
  • Detailed Comments
  • Entering comments with eGroupWare

• Lecture 13: Hybrid Reconfigurable Systems
  • Chameleon Multi-context reconfigurable logic
  • CMU Piperench
  • CMU Queue Machines
  • Tensilica Configurable SOC Processor Core

• Lecture 14: Final Projects
  • Goals of the final project
  • Helpful hints
  • Grading