CSE 566
Fall 2004 Reconfigurable System On Chip Design John W. Lockwood

Course Schedule

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Tuesday Thursday

Tue. Sep 7

First Day of Class
Lecture 1: Introduction to Reconfigurable System On Chip Design
Assigned Reading:

Embedded System Design: Chapter 1

Thr. Sep 9 (Lecture)

Lecture 2: Logic and Integrated Circuit Technologies
Assigned Reading:

Embedded System Design: Chapter 2.1-2.3

Homework 1 Assigned

Tue. Sep 14

Lecture 3: Language-based Hardware Designs
Demonstration of eGroupWare
Assigned Reading:

Introductory VHDL: Chapters 1, 2 and 3

Thr. Sep 16 (Lecture)

Lecture 4: Synchronous Storage & Finite State Machines
Assigned Reading:

Introductory VHDL: Chapters 4 and 5
(Only sections 4.1, 5.1-5.8)

Homework 1 Due

Submit on-line on Friday by 5pm.

Tue. Sep 21

Lecture 5: Management of Large-Scale SoC Project Designs with Concurrent Versions System (CVS)
Assigned Reading:

CVS Manual: Chapters 1 - 2.5
Evolvable Internet Hardware Platforms, by John W. Lockwood, NASA/DoD Workshop on Evolvable Hardware (EHW'01), Long Beach, CA, July 12-14, 2001, pp. 271-279.

Machine Problem 0 Assigned:
Thr. Sep 23 (Laboratory Session)

Assigned Reading:

TCP Processor: Design, Implementation, Operation, and Usage, by David Schuehler, Washington University in St. Louis Technical Report: WUCSE-2004-53, September 15, 2004
Chapters 1 - 5.3

Machine Problem 1 Assigned

Tue. Sep 28 (Laboratory Session)

Lecture 6: Transmission Control Protocol / Internet Protocol (TCP/IP) Processing with Layered Wrappers
Assigned Reading:

Introductory VHDL: Chapter 7
A Modular System for FPGA-based TCP Flow Processing in High-Speed Networks

Machine Problem 0 Due:

MP0: Version Control for Large-Scale SoC Project Designs
Submit to CVS by 2:30pm

Thr. Sep 30 (Laboratory Session)

Assigned Reading:

Introductory VHDL: Chapter 8

TCP Processor: Design, Implementation, Operation, and Usage,
Chapters 5.4, 6, 7.

Machine Problem 1 Due:

MP1: Simulation of a TCP/IP PortTracking Module
Submit to CVS by 2:30pm

Tue. Oct. 5 (Laboratory Session)

Lecture 7: Scanning Data with the Transmission Control Protocol / Internet Protocol (TCP/IP) Wrappers
Assigned Reading:

Architecture for a Hardware Based, TCP/IP Content Scanning System, by David V. Schuehler, James Moscola, and John W. Lockwood; Hot Interconnects 11 (HotI), Stanford, CA, USA, pp. 89-94, Aug. 2003.

Homework 2 Assigned
Thr. Oct 7 (Laboratory Session)

Homework 2 Due

Submit on-line on Friday by 5pm.

Tue. Oct. 12 (Lecture)

Lecture 8: Content Analysis with the Scan Module
Assigned Reading:

Review manual page for TCPDump

Homework 2 returned
Thr. Oct 14 (Lecture)

Lecture 9: COREs: Logic cores, Commercial cores, core Generators, OpenCores.org
Assigned Reading:

Existing code for MP2 (available via CVS)

Homework 3 Assigned

Tue. Oct. 19 (Lecture)

Lecture 10: Random Access Memories, BlockRAMs, SRAMs, SDRAMS
MP1 returned (score via email)
Homework 3 Due
Thr. Oct 21 (Lecture)

Lecture 11: Pipelines and Retiming
Machine Problem 2 Assigned

Tue. Oct. 26 (Lecture)

Discuss CSE566 Final Projects
Lecture 12: Using the TCP Processor:
Guest Lecture by Dave Schuehler
Thr. Oct 28 (Lab)

Work on Machine Problem 2

Tue. Nov 2 (Lecture)

Discuss CSE566 Final Projects
Lecture 13: Robust TCP reassembly in the Presence of Adversaries
Guest Lecture by Sarang Dharmapurikar
Thr. Nov 4 (Lab)

Lecture 14: Final Project Template
Final Project Template in PowerPoint format

Tue. Nov 9 (Lecture)

Present Project Pitch Due

Use Final Project Template
Upload DAC-ready draft to Gradebot with:
Assignment="Final Design Plan"

Lecture 15: Laboratory Configuration for Hardware Testing
Thr. Nov 11 (Lab)

Machine Problem 2 Due

Tue. Nov 16 (Lecture)

Present Final Project:
Status Report 1

Upload all Project presentation slides (as PPT) to Gradebot with:
Assignment="Status 1"
Present new slides in class on Tuesday

Lecture 16: Peer Evaluations
Thr. Nov 18 (Lab)

Work on Final Projects

Tue. Nov 23 (Lecture)

Present Final Project:
Status Report 2

Upload all Project presentation slides (as PPT) to Gradebot with:
Assignment="Status 2"
Present new slides in class on Tuesday

Thr. Nov 25

Thanksgiving
(no class)

Tue. Nov 30 (Lecture)

Final Project: Writeup Draft Due

Template Document (.doc)
Upload writeup to Gradebot with:
Assignment="Final Project Writeup"
Discuss writeup with Prof. Lockwood

Thr. Dec 2

Upload REVISED writeup to Gradebot with:
Assignment="Final Project Writeup"
Discuss writeup with Prof. Lockwood

Tue. Dec 7 (Lecture)

Final Project: Writeup Due

Upload DAC-ready writeup to Gradebot with:
Assignment="Final Project Writeup"
Submit entry to DAC Student Design Contest by 5pm

Thr. Dec 9

Work on Final Projects

Tue. Dec 14 (Lecture)

Final Project: Hardware Demonstrations

Upload final PowerPoint Gradebot with: Assignment="Final Project Presentation Slides"
Present project to class for Peer-Evaluation grades

Thr. Dec 16

Final Project Submission

Create .zip file with VHDL source code, system software, and project makefiles, then upload to Gradebot with: Assignment="Final Project VHDL and Syn/Sim scripts"

MONDAY Dec 20 (Final)

MidTerm Exam: 1-3pm

All material in lectures
All material in readings
All material in homeworks
All material in machine problems
All material discussed for final projects (all teams)

Copyright 2004
John W. Lockwood
Washington University
Saint Louis, MO

Tuesday	Thursday
Tue. Sep 7 First Day of Class Lecture 1: Introduction to Reconfigurable System On Chip Design Assigned Reading: Embedded System Design: Chapter 1	Thr. Sep 9 (Lecture) Lecture 2: Logic and Integrated Circuit Technologies Assigned Reading: Embedded System Design: Chapter 2.1-2.3 Homework 1 Assigned
Tue. Sep 14 Lecture 3: Language-based Hardware Designs Demonstration of eGroupWare Assigned Reading: Introductory VHDL: Chapters 1, 2 and 3	Thr. Sep 16 (Lecture) Lecture 4: Synchronous Storage & Finite State Machines Assigned Reading: Introductory VHDL: Chapters 4 and 5 (Only sections 4.1, 5.1-5.8) Homework 1 Due Submit on-line on Friday by 5pm.
Tue. Sep 21 Lecture 5: Management of Large-Scale SoC Project Designs with Concurrent Versions System (CVS) Assigned Reading: CVS Manual: Chapters 1 - 2.5 Evolvable Internet Hardware Platforms, by John W. Lockwood, NASA/DoD Workshop on Evolvable Hardware (EHW'01), Long Beach, CA, July 12-14, 2001, pp. 271-279. Machine Problem 0 Assigned:	Thr. Sep 23 (Laboratory Session) Assigned Reading: TCP Processor: Design, Implementation, Operation, and Usage, by David Schuehler, Washington University in St. Louis Technical Report: WUCSE-2004-53, September 15, 2004 Chapters 1 - 5.3 Machine Problem 1 Assigned
Tue. Sep 28 (Laboratory Session) Lecture 6: Transmission Control Protocol / Internet Protocol (TCP/IP) Processing with Layered Wrappers Assigned Reading: Introductory VHDL: Chapter 7 A Modular System for FPGA-based TCP Flow Processing in High-Speed Networks Machine Problem 0 Due: MP0: Version Control for Large-Scale SoC Project Designs Submit to CVS by 2:30pm	Thr. Sep 30 (Laboratory Session) Assigned Reading: Introductory VHDL: Chapter 8 TCP Processor: Design, Implementation, Operation, and Usage, Chapters 5.4, 6, 7. Machine Problem 1 Due: MP1: Simulation of a TCP/IP PortTracking Module Submit to CVS by 2:30pm
Tue. Oct. 5 (Laboratory Session) Lecture 7: Scanning Data with the Transmission Control Protocol / Internet Protocol (TCP/IP) Wrappers Assigned Reading: Architecture for a Hardware Based, TCP/IP Content Scanning System, by David V. Schuehler, James Moscola, and John W. Lockwood; Hot Interconnects 11 (HotI), Stanford, CA, USA, pp. 89-94, Aug. 2003. Homework 2 Assigned	Thr. Oct 7 (Laboratory Session) Homework 2 Due Submit on-line on Friday by 5pm.
Tue. Oct. 12 (Lecture) Lecture 8: Content Analysis with the Scan Module Assigned Reading: Review manual page for TCPDump Homework 2 returned	Thr. Oct 14 (Lecture) Lecture 9: COREs: Logic cores, Commercial cores, core Generators, OpenCores.org Assigned Reading: Existing code for MP2 (available via CVS) Homework 3 Assigned
Tue. Oct. 19 (Lecture) Lecture 10: Random Access Memories, BlockRAMs, SRAMs, SDRAMS MP1 returned (score via email) Homework 3 Due	Thr. Oct 21 (Lecture) Lecture 11: Pipelines and Retiming Machine Problem 2 Assigned
Tue. Oct. 26 (Lecture) Discuss CSE566 Final Projects Lecture 12: Using the TCP Processor: Guest Lecture by Dave Schuehler	Thr. Oct 28 (Lab) Work on Machine Problem 2
Tue. Nov 2 (Lecture) Discuss CSE566 Final Projects Lecture 13: Robust TCP reassembly in the Presence of Adversaries Guest Lecture by Sarang Dharmapurikar	Thr. Nov 4 (Lab) Lecture 14: Final Project Template Final Project Template in PowerPoint format
Tue. Nov 9 (Lecture) Present Project Pitch Due Use Final Project Template Upload DAC-ready draft to Gradebot with: Assignment="Final Design Plan" Lecture 15: Laboratory Configuration for Hardware Testing	Thr. Nov 11 (Lab) Machine Problem 2 Due
Tue. Nov 16 (Lecture) Present Final Project: Status Report 1 Upload all Project presentation slides (as PPT) to Gradebot with: Assignment="Status 1" Present new slides in class on Tuesday Lecture 16: Peer Evaluations	Thr. Nov 18 (Lab) Work on Final Projects
Tue. Nov 23 (Lecture) Present Final Project: Status Report 2 Upload all Project presentation slides (as PPT) to Gradebot with: Assignment="Status 2" Present new slides in class on Tuesday	Thr. Nov 25 Thanksgiving (no class)
Tue. Nov 30 (Lecture) Final Project: Writeup Draft Due Template Document (.doc) Upload writeup to Gradebot with: Assignment="Final Project Writeup" Discuss writeup with Prof. Lockwood	Thr. Dec 2 Upload REVISED writeup to Gradebot with: Assignment="Final Project Writeup" Discuss writeup with Prof. Lockwood
Tue. Dec 7 (Lecture) Final Project: Writeup Due Upload DAC-ready writeup to Gradebot with: Assignment="Final Project Writeup" Submit entry to DAC Student Design Contest by 5pm	Thr. Dec 9 Work on Final Projects
Tue. Dec 14 (Lecture) Final Project: Hardware Demonstrations Upload final PowerPoint Gradebot with: Assignment="Final Project Presentation Slides" Present project to class for Peer-Evaluation grades	Thr. Dec 16 Final Project Submission Create .zip file with VHDL source code, system software, and project makefiles, then upload to Gradebot with: Assignment="Final Project VHDL and Syn/Sim scripts"
MONDAY Dec 20 (Final) MidTerm Exam: 1-3pm All material in lectures All material in readings All material in homeworks All material in machine problems All material discussed for final projects (all teams)