CSE 566M Fall 2006

Reconfigurable System on Chip Design

John W. Lockwood

ABSTRACT

• Complete computing and networking systems can be implemented within a single Integrated Circuit (IC). Such a system consists of multiple components interconnected by common infrastructure. This class will explore the challenges to design and test a complete System-on-Chip (SoC). Exercises will be given to design, synthesize, and simulate components using modern Computer Aided Design (CAD) tools. Resulting systems will be prototyped in reprogrammable hardware.

INSTRUCTOR

• Prof. John W. Lockwood
  • Email: lockwood@arl.wustl.edu
    
  • Office Hours: By appointment
  • Office Location: Bryan 522F

LABORATORY ASSISTANTS

• Richard Hough

PREREQUISITE

• Experience with hardware design and VHDL synthesis
  • EE260/CS260M, CoE/EE/CS362, CoE/EE/462 or equivalent
• Experience with computer networks
  • CS423S, CS533M, or equivalent

TIMES & LOCATIONS

• Lecture/Laboratory
  • Time: Tuesday & Thursday: 2:37pm - 4:00pm
  • Location: Urbauer 116

WEBSITE

• http://www.arl.wustl.edu/~lockwood/class/cse566-f06/

OUTLINE

• Review techniques to implement combinational logic and finite state machines
• Introduce Reconfigurable System On Chip (SoC) Design Methodology
• Synthesize components of SOC systems
• Integrate modular hardware components
• Implement machine problems to perform assigned streaming processing fucntions in FPGA hardware
• Implement final project to perform customized streaming processing functions in FPGA hardware

TEXTBOOKS/READING

• Reference Textbooks
  • Frank Vahid and Tony Givargis, Embedded System Design: A Unified Hardware/Software Introduction, 2002, Wiley, ISBN 0-471-38678-2.
  • Sudhakar Yalamanchili, Introductory VHDL: From Simulation to Synthesis, 2001, ISBN 0-13-080982-9

• Select Readings from networking conferences and journals
  • CVS Manual
  • Evolvable Internet Hardware Platforms, by John W. Lockwood, NASA/DoD Workshop on Evolvable Hardware (EHW'01), Long Beach, CA, July 12-14, 2001, pp. 271-279.
  • An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall, by John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, and David Lim; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Paper 14B, Sep 1-3, 2003.

SOFTWARE TOOLS

• ModelSim: Compiler / Simulator
• Synplicity: Hardware Synthesis
• Celoxica: Handel-C Tools
• Impulse: Impulse C Tools.
• Xilinx: FPGA Backend Tools
• Cygwin Tools: GNU Software (g++/gcc)

CREDITS

• 3 units

GRADING

• Homeworks (20%)
• Machine Problems (20%)
• Midterm (20%)
• Final Project (40%)

LATE POLICY

• It is important to submit assignments on-time.
• As with time-to-market considerations, the value of a late submission decreases quickly with time.
• Points will be deducted at a rate of 1 points per hour for homeworks or machine problems that are not submitted on-time.