Homework Assignment 1

Instructions

• Use the document editor of your choice to electronically generate solutions to your homework.

• Save your homework solutions as: a text (.txt), web page (.html), Acrobat (.pdf), or Word (.doc) document

• Upload your homework to the Gradebot Server

  Homework Questions

  1. Define the following terms in the context of integrated circuit design. Spell out the acronym (where needed) and provide a 1-sentance (or longer) definition. (15 pts)
     • SoC

     • ASIC

     • CAD

     • NRE

     • FPGA

     • FSM

     • VHDL

     • RTL

     • bottom-up

     • top-down

     • CMOS

     • LUT

     • CLB

     • ALU

  2. Suppose that your company must decide between fabricating a Million-gate custom Integrated Circuit or implementing the same logic on a Field Programmable Gate Array (FPGA). You are given the following parameters
     • Custom IC has NRE cost of $2,000,000
     • Custom IC has a per-unit cost of $50
     • Low-Cost FPGA has a per-unit cost of $100
     • High-Performance FPGA has NRE cost of $500
     Based only on the parameters above, How many devices would your company need to fabricate in order to build the custom IC with break-even cost as compared to the FPGA? Show your work. (4 pts)
     
     
     
     
     
     
     
     
  3. Suppose that your company is preparing to release a new System-On-Chip that has a market window of 36 months. It is projected that, during the ramp-up period of market growth, the monthly revenue for the product will will increase by $500,000 per month (starting at zero). Peak revenue for the device is projected to occur at 18 months, and decline thereafter during the ramp-down period to zero. Use the simplified revenue model described in the lecture notes to compute revenue over the lifetime of the product.(4 pts)
     
     
     • Compute the revenue your company should expect if the product is brought to market without delay
       
       
       
     • Compute the revenue your company should expect if the product is brought to market with 6 months of time-to-market.
       
       
       
     • Compute the revenue your company should expect if the product is brought to market with 12 months of time-to-market.
       
       
       
     • Compute the revenue your company should expect if the product is brought to market with 18 months of time-to-market.
       
       
       

  4. Given that Moore's law predicted doubling of the size of a manufacturable ICs every 18 months, how many times more transistors have ICs gained over a period of 30 years? (4 pts)
     
     
     
     
     
  5. Describe the limitations of Moore's law and explain why it can't hold forever. (2 pts)
     
     
     
     
  6. How many transistors are required to implement a a 4-input CMOS NOR gate using a minimum number of NMOS and PMOS transitors. Explain. (2 pts).
     
     
     
     
     
     
     
     
  7. Complete the table below for the following
     4-input LUT that implements the function:
     (a*b)+(c*d) 4 pts

     a	b	c	d	F
     0	0	0	0	___
     0	0	0	1	___
     0	0	1	0	___
     0	0	1	1	___
     0	1	0	0	___
     0	1	0	1	___
     0	1	1	0	___
     0	1	1	1	___
     1	0	0	0	___
     1	0	0	1	___
     1	0	1	0	___
     1	0	1	1	___
     1	1	0	0	___
     1	1	0	1	___
     1	1	1	0	___
     1	1	1	1	___

  8. Design a Finite State Machine (FSM) that performs the hardware-accelerated Ebay server, as described in class.
     • Inputs and outputs are defined by the VHDL entity below:

       ENTITY auction IS PORT ( clk: IN std_logic; -- Use rising edge Reset: IN std_logic; -- Active high (pulled to '1' at start, then '0' otherwise) Duration: IN std_logic_vector(23 DOWNTO 0); -- Length of the auction, in seconds Time_Left: OUT std_logic_vector(23 DOWNTO 0); -- Remaining time left for the auction Bid_Enable: IN std_logic; -- indicates that a bid has arrived Bid_Amount: IN std_logic_vector(19 DOWNTO 0); -- Amount of the bid. $Unsigned Win_Amount: OUT std_logic_vector(19 DOWNTO 0); -- Current winning amount. $Unsigned Bidder_ID: IN std_logic_vector(31 DOWNTO 0); -- Identifier of a user with highest bid Winner_id: OUT std_logic_vector(31 DOWNTO 0); -- Identifier of the winner (default=0) END auction;

     • Start by Drawing a State Transition Diagram for the state machine(s) that implement your system.

     • Write VHDL source code that is
       • complete
       • synthesizable
       • fully debugged

     • Use ModelSim to simulate
       • Reset
       • A winning Bid
       • A losing Bid
       • A bid after the time has run out

     • Save screenshots that show that the circuit is operational