Homework Assignment 2 (revised)

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  Homework Questions

  Part 1 of 2 - Based on the material in the paper :

  System-On-Chip: Reuse and Integration, by Resve Saleh, Steve Wilton, Shahriar Mirabbasi, Alan Hu, Mark Greenstreet, Guy Lemieux, Partha Pratim Pande, Christian Grecu, and Andre Inanov; IEEE Proceedings, Vol. 94, No. 6, June 2006, pp. 1050-1069
  1. Explain why reusable design components are critical as by-product of Moore's law
     

  2. Define the term SoP and give an example.

  3. Define the term SoB and give an example.

  4. Compare and contrast the similarities and differences between:
     • Soft IP blocks

       
       

     • Hard IP blocks

       
       

     • Firm IP blocks

       
       

  5. Define the term AMS and give an example of a real-life device that uses AMS.

     
     

  6. List the key features of a platform-based design.

     
     

  7. Describe the condition under which a metastable state could occur on a SoC

     
     

  8. Consider NoC topologies in the paper that can transfer data between a 16-core multiprocessor
     • Which configuration(s) require up to 3 switching hops.
       

     • Which configuration(s) require up to 5 switching hops.
       

     • Which configuration(s) require up to 7 switching hops.
       

  9. What is the purpose and what is contained in header Flit?
     

  10. Explain why virual channel buffers are used on a NoC switch
      

  11. Describe the function of a test pattern source and sink
      

  12. Explain why BIST simplifies the verification of a SoC
      

  13. Given that the probability, p, that a given IP core my have an error is 4% (i.e., p=0.04), what is the probablity that a SoC with 16 IP cores will have no faults?
      

  14. Describe the main idea behind compositional model checking.
      

      Part 2/2 - Based on content from the OpenCores.org website

  15. Describe the function and implementation of the fpu100 core. In particular:
      What category of function does the FPU core perform?

  16. In what language was the FPU core written?

  17. Which five operations are supported?

  18. Describe the function and implementation of the 128/192 AES core. In particular:
      What category of function does the AES core perform?

  19. In what langauge was the source code for the AES core written

  20. What standard interface is used to interface the AES core to a SoC?

  21. Describe the function and implementation of the T80 cpu. In particular:
      With what instruction set is the processor compatible ?

  22. According to the FAQ for the FPGA Arcade project, what synthesiser can be used to build the circuits that get the games running?