CSE 260. Introduction to Digital Logic and Computer Design

Spring 2014

This course teaches how digital circuits are designed and provides an introduction to how computers work. Students learn to use hardware description languages and computer-aided design tools (simulation, circuit synthesis) and apply them to the design of a variety of digital circuits. Circuits are simulated and prototyped in the lab, allowing students to see how abstract design concepts can be translated into real, working circuits. The course explores the underlying limitations on the performance of digital circuits and explains how performance can be improved. Students learn how designs can be optimized for lower cost and how to make basic design trade-offs between circuit cost and performance. The course presents the design of a general-purpose processor, allowing students to learn how computers work at fundamental level, and providing opportunities for machine-level programming and for extending the processor to add functionality and improve performance. Prerequisites: CSE 131 or 126 or comparable programming experience. Credit: 3 units.


Class Preparation. There is a reading assignment for each class. You are expected to complete the assigned reading before each class. In addition, there is a set of assigned review questions that must be turned in at the start of each class. These will be collected and checked to make sure that you made a serious effort, but will not be graded for correctness, or returned. Also, for each question, I will select one student to explain their answer that question, at the beginning of class. Most of our class time will be devoted to working problems based on the assigned reading. I've found that this is generally much more productive than using class time for lecturing, but it does require that you come to class prepared. Of course, if you have questions about the reading assignment, do not hesitate to ask, either at the start of class, or before class using the online discussion forum.

Labs and Studios. The class includes a series of laboratory exercises that involve the use of computer-aided design tools to design and simulate circuits to solve particular problems. Many of the labs will include a component, where you implement your design on an FPGA prototype board and test it. Five labs will be assigned during the semester. See the schedule below for specifics. The labs can require a substantial amount of time and effort. Do not leave them to the last minute.

To help you prepare for the labs, there will be optional studio sessions before each lab is due. The scheduled lab times will be used for these studios. In studios, you will work in groups on a series of exercises designed to help you get familiar with the material you will need for the lab. You are not required to attend a studio, but if you do, you will probably find that it saves you time and effort. The Tuesday and Friday studios will be in Urbauer 218. The Thursday studio will be in Urbauer 214.

SVN repositories have been setup for each student registered for the class. All source files needed for labs and studios will be made available in the repositories, and electronic copies of your modified sources for labs must be committed to the repository.

Quizes. There will be a quiz every two weeks on Tuesdays. The first will be on January 21. Each quiz will address material that has been covered since the last quiz or exam. Quizes will be given at the beginning of class, so don't be late. There will be no makeups, but your low quiz score will be dropped from your course grade.

Examinations. There will be three exams given during the semester. The first two will be in class on February 13 and March 27. The final exam will be May 7, 3:30-5:30. THERE WILL BE NO ALTERNATE TIMES FOR ANY OF THE EXAMS - IT IS UP TO YOU TO ARRANGE YOUR OTHER ACTIVITIES TO AVOID CONFLICTS.

Textbook. We will be using an online textbook for the course. A partial draft is available here and updates will be posted as the semester progresses. The book has been formatted to be read conveniently on an iPad or other tablet. Here is a second version formatted to be printed on standard printer paper, with two pages per side.

Working with Others Students. You are encouraged to work with other students in study groups, so that you can help each other master the course material. However, unless otherwise specified, all work that is to be handed in must be done individually. This includes answers to review questions and labs. You may discuss general approaches with your fellow students, and the TAs will provide hints and general guidance. However, you are expected to turn in your own work and only your own work. You should not share your solutions with other students. Sharing of block diagrams, VHDL code, simulation output or any other written material is expressly forbidden. Any group of students found to have collaborated inappropriately on an assignment will have the full value of the assignment deducted from the grades of all students involved. Repeat offenses will not be treated so leniently.

Late Policy. Review questions and written lab reports are due in class on the day assigned. Electronic copies of lab submissions must be committed to your svn repository by 6:00 pm on the due date. Late submissions will not be accepted, not even for partial credit. No exceptions. If, for some reason, you cannot make it to class, you may turn in your assignment in the CSE department office, by giving it to one of the office staff, and asking them to initial and date it. It must be turned in before class. This is to be used in exceptional circumstances only. Do not make a habit of it.

Expectations. This course covers a great deal of material and you will need to devote substantial time and effort to mastering it. You should plan to spend an average of eight to ten hours per week outside of class.

On-line Communication. Most information about the course can be obtained electronically. In addition to this web site, there is a Piazza discussion group which you can access using a web browser. I urge you to use Piazza to post questions you may have about lecture material, problem sets and design problems. You may also feel free to post general comments about the course material or to respond to questions from other students. The more you use it, the more valuable it will be to both you and your fellow students. The TAs and I will monitor Piazza regularly and answer questions, and provide guidance (and occasional hints) on labs. We will also use it to post clarifications and corrections and to make general announcements, so you should check it regularly.

Computer Aided Design Tools. The course makes extensive use of the Xilinx CAD tools. The tools we use are available on all CEC computers and can be accessed remotely by using Remote Desktop to login to the Windows server, oasis.cec.wustl.edu. Alternatively, the tools can be downloaded for free from the Xilinx web site. The tools can be run under Windows or Linux (fedora enterprise). There is no Mac version, but they can be run in a Windows or Linux virtual machine on newer Macs, using a virtualization package, such as VM-ware or Virtual Box.

Consulting Hours. The primary role of the TAs in this course is to help you learn the material, by holding consulting hours. Their schedule is posted below. Note that the last two columns show where the TAs will hold their consulting hours. This is different during weeks when labs are due than during weeks when no labs are due. For the first lab only, all consulting hours will be in Urbauer 215 (this is a simulation-only lab).

DayTimeWhonon-lab week locationlab week location
Sunday4:00-6:00Tayloroutside Bryan 503Bryan 316
Monday1:00-2:30KevinBryan 522Bryan 316
Tuesday10:00-11:30JeremyBryan 522Bryan 316
Tuesday11:30-1:00TroyBryan 522Bryan 316

Lectures and Assignments

The course is organized into three sections, as shown below. Note dates for quizes and labs. Reading assignments refer to chapters from the online text. Review questions are due in class, on the days shown below. So for example, the review questions for chapter 2 are due on 1/16.

First Half

Date Title Required Reading Review Questions Assignments Due
1/14 Introduction to Digital Logic Design and Computer Systems Chapter 1 -
1/16 First Steps Chapter 2 .docx, .pdf -
1/21 VHDL - Part 1 Chapter 3, plus 5.4 .docx, .pdf quiz 1, solution
1/23 Computer Aided Design Tools Chapter 4 .docx, .pdf -
1/28 VHDL - Part 2 Chapter 5 .docx, .pdf lab1, solution
1/30 Building Blocks of Digital Circuits Chapter 6 .docx, .pdf -
2/4 Sequential Circuits - Part 1 Chapter 7 .docx, .pdf quiz 2, solution
2/6 Sequential Circuits - Part 2 Chapter 8 .docx, .pdf -
2/11 Review Session - - -

Second Half

Date Title Required Reading Review Questions Assignments Due
2/18 VHDL - Part 3 Chapter 9 .docx, .pdf lab2, solution
2/20 Design Studies - Part 1 Chapter 10 .docx, .pdf -
2/25 Design Verification Chapter 11 .docx, .pdf quiz 3, solution -
2/27 Design Studies - Part 2 Chapter 12 .docx, .pdf -
3/4 Design Optimization - Part 1 Chapter 13 .docx, .pdf lab3, solution
3/6 Design Studies - Part 3 Chapter 14 .docx, .pdf -
3/18 Implementing Circuit Elements Chapter 15 .docx, .pdf quiz 4, solution
3/20 Timing Issues in Digital Circuits Chapter 16, Metastabilty .docx, .pdf -
3/25 Review Session - - -

Third Half

Date Title Required Reading Review Questions Assignments Due
4/1 Design of the WashU-2 - Part 1 Chapter 17 .docx, .pdf lab4, solution
4/3 Design of the WashU-2 - Part 2 Chapter 18 .docx, .pdf -
4/8 Design of the WashU-2 - Part 3 Chapter 19 .docx, .pdf quiz 5, solution
4/10 Memory Systems Chapter 20 .docx, .pdf -
4/15 Improving Processor Performance - Part 1 Chapter 21 .docx, .pdf -
4/17 Improving Processor Performance - Part 2 Chapter 22 .docx, .pdf -
4/22 Design Optimization - Part 2 Chapter 23 .docx, .pdf quiz 6, solution
4/24 Design Optimization - Part 3 Chapter 24 .docx, .pdf -
tba Review Session - - -
5/1 - - - lab5, solution